3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical...3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical structure with high-aspect ratio.Obviously top-down images is not enough for process control,instead inner structure control becomes much more important than before,e.g.channel hole profiles.Besides,multi-layers,special materials and YMTC unique X-Tacking technology also bring other metrology challenges:high wafer bow,stress induced overlay,opaque film measurement.Technical development can adopt some destructive methodology(TEM,etch-back SEM),while manufacturing can only use nondestructive method.These drive some new metrology development,including X-Ray,mass measure and Mid-IR spectroscopy.As 3D NAND suppliers move to>150 layers devices,the existing metrology tools will be pushed to the limits.Still,the metrology must innovate.展开更多
3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are es...3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance,higher bit density,and at lower cost.Current 3D NAND technology involves process steps that form array and peripheral CMOS(Complementary Metal-Oxide-Semiconductor)regions side-by-side,resulting in waste of silicon real estate and film stress compromises,and limits the paths of making advanced 3D NAND devices.An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through metal VIAs(Vertical Interconnect Access)[1].Highly accurate and efficient metrology is required to monitor VIA interface due to increased process complexity and precision requirements.With the advanced processing of AFM(Atomic Force Microscopy)images,highly accurate and precise measurements have been achieved.An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.展开更多
基金The authors would like to thank all YMTC metrology vendors for helping with tool evaluation,data collection and data analysis.
文摘3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical structure with high-aspect ratio.Obviously top-down images is not enough for process control,instead inner structure control becomes much more important than before,e.g.channel hole profiles.Besides,multi-layers,special materials and YMTC unique X-Tacking technology also bring other metrology challenges:high wafer bow,stress induced overlay,opaque film measurement.Technical development can adopt some destructive methodology(TEM,etch-back SEM),while manufacturing can only use nondestructive method.These drive some new metrology development,including X-Ray,mass measure and Mid-IR spectroscopy.As 3D NAND suppliers move to>150 layers devices,the existing metrology tools will be pushed to the limits.Still,the metrology must innovate.
文摘3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance,higher bit density,and at lower cost.Current 3D NAND technology involves process steps that form array and peripheral CMOS(Complementary Metal-Oxide-Semiconductor)regions side-by-side,resulting in waste of silicon real estate and film stress compromises,and limits the paths of making advanced 3D NAND devices.An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through metal VIAs(Vertical Interconnect Access)[1].Highly accurate and efficient metrology is required to monitor VIA interface due to increased process complexity and precision requirements.With the advanced processing of AFM(Atomic Force Microscopy)images,highly accurate and precise measurements have been achieved.An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.
