Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

With the rapid development of machine learning,the demand for high-efficient computing becomes more and more urgent.To break the bottleneck of the traditional Von Neumann architecture,computing-in-memory(CIM)has attracted increasing attention in recent years.In this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring continuous weight updating in online training,a flash-based computing-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is investigated.On the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and accuracy.On the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved computing accuracy.Even after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale computing ability of memory.Further characterizations are done on read disturb to demonstrate its robust reliabilities.By processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 NN.Our results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

Flash-based in-memory computing for stochastic computing in image edge detection

The“memory wall”of traditional von Neumann computing systems severely restricts the efficiency of data-intensive task execution,while in-memory computing(IMC)architecture is a promising approach to breaking the bottleneck.Although variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures,stochastic computing(SC)can compensate for these shortcomings due to its low sensitivity to cell disturbances.Furthermore,massive parallel computing can be processed to improve the speed and efficiency of the system.In this paper,by designing logic functions in NOR flash arrays,SC in IMC for the image edge detection is realized,demonstrating ultra-low computational complexity and power consumption(25.5 fJ/pixel at 2-bit sequence length).More impressively,the noise immunity is 6 times higher than that of the traditional binary method,showing good tolerances to cell variation and reliability degradation when implementing massive parallel computation in the array.

A gate-tunable artificial synapse based on vertically assembled van der Waals ferroelectric heterojunction

Memtransistor,a multi-terminal device that combines both the characteristics of a memristor and a transistor,has been intensively studied in two-dimensional layered materials(2 DLM),which show potential for applications in such as neuromorphic computation.However,while often based on the migration of ions or atomic defects in the conduction channels,performances of memtransistors suffer from the poor reliability and tunability.Furthermore,those known 2 DLM-based memtransistors are mostly constructed in a lateral manner,which hinders the further increasing of the transistor densities per area.Until now,fabricating non-atomic-diffusion based memtransistors with vertical structure remains challenging.Here,we demonstrate a vertically-integrated ferroelectric memristor by hetero-integrating the 2 D ferroelectric materials CuInP_(2)S_(6)(CIPS)into a graphite/CuInP_(2)S_(6)/MoS_(2)vertical heterostructure.Memristive behaviour and multi-level resistance states were realized.Essential synaptic behaviours including excitatory postsynaptic current,paired-pulse-facilitation,and spike-amplitude-dependent plasticity are successfully mimicked.Moreover,by applying a gate potential,the memristive behaviour and synaptic features can be effectively gate tuned.Our findings pave the way for the realization of novel gate-tunable ferroelectric synaptic devices with the capability to perform complex neural functions.