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An advanced SEU tolerant latch based on error detection 被引量:5
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作者 Hui Xu Jianwei Zhu +1 位作者 Xiaoping Lu jingzhao li 《Journal of Semiconductors》 EI CAS CSCD 2018年第5期77-80,共4页
This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error d... This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the C-element.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5%less energy and 33.1%less propagation delay than the triple modular redundancy(TMR)latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively. 展开更多
关键词 single event upset(SEU) latch error detection stacked
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