Scarcity of cadaveric liver donors compared with the large number of patients with liver disease has been considered the main obstacle to use liver transplantation(LT)to treat hepatic malignancies and for the developm...Scarcity of cadaveric liver donors compared with the large number of patients with liver disease has been considered the main obstacle to use liver transplantation(LT)to treat hepatic malignancies and for the development of transplant oncology.It is known that we are experiencing a true paradigm shift in the fundamental problem of transplantology,which is none other than the imbalance between donation and graft implants(1).Because the most common indication of LT in most countries[hepatitis C virus(HCV)cirrhosis]has started to decrease in the waiting lists(2,3).One might think that,for the first time in many years in Western countries,we could find a higher supply of organs than recipients for them.展开更多
Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fau...Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model （PDFM）, which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applica- tions （graphic, video, digital filtering, etc.）, errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excita- tion, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage fre- quency scaling circuits with tolerable error rates.展开更多
文摘Scarcity of cadaveric liver donors compared with the large number of patients with liver disease has been considered the main obstacle to use liver transplantation(LT)to treat hepatic malignancies and for the development of transplant oncology.It is known that we are experiencing a true paradigm shift in the fundamental problem of transplantology,which is none other than the imbalance between donation and graft implants(1).Because the most common indication of LT in most countries[hepatitis C virus(HCV)cirrhosis]has started to decrease in the waiting lists(2,3).One might think that,for the first time in many years in Western countries,we could find a higher supply of organs than recipients for them.
基金Supported in part by the National Natural Science Foundation of China (No. 60236020)the MCyT and FEDER Projects TEC2010
文摘Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model （PDFM）, which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applica- tions （graphic, video, digital filtering, etc.）, errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excita- tion, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage fre- quency scaling circuits with tolerable error rates.
