Power management unit chip design for automobile active-matrix organic light-emitting diode display module

A power management unit (PMU) chip supplying dual panel supply voltage, which has a low electro-magnetic interference (EMI) characteristic and is favorable for miniaturization, is designed. A two-phase charge pump circuit using external pumping capacitor increases its pumping current and works out the charge-loss problem by using bulk-potential biasing circuit. A low-power start-up circuit is also proposed to reduce the power consumption of the band-gap reference voltage generator. And the ring oscillator used in the ELVSS power circuit is designed with logic devices by supplying the logic power supply to reduce the layout area. The PMU chip is designed with MagnaChip’s 0.25 μm high-voltage process. The driving currents of ELVDD and ELVSS are more than 50 mA when a SPICE simulation is done.

Design of logic process based low-power 512-bit EEPROM for UHF RFID tag chip

A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.

Design of small-area multi-bit antifuse-type 1 kbit OTP memory

A multi-bit antifuse-type one-time programmable (OTP) memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS (complementary metal-oxide semiconductor) process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm×327 μm, and the read current is simulated to be 30.4 μA.

干骺端固定解剖型非骨水泥柄结合陶瓷对陶瓷全髋关节置换治疗30岁以下患者的临床结果

年轻患者全髋关节置换手术方式还存在争议。作者分析了96例（127髋）30岁以下患者采用干骺端固定解剖型非骨水泥柄结合陶瓷对陶瓷全髋关节置换的治疗结果。随访10～16年，Harris评分、WOMAC评分、UCLA评分分别为95、16、8分。手术1年后，没有发生疼痛，所有股骨柄均未发现松动。无关节异响、陶瓷碎裂、松动以及骨溶解等并发症。因此作者认为，

骨水泥型与非骨水泥型全膝关节置换,哪个更佳?

为了对比骨水泥型与非骨水泥型全膝关节置换的治疗效果，作者进行了一项前瞻性随机研究，纳入行双侧膝关节置换且年龄＜55岁的患者80例（160膝），女性63例，男性17例，平均年龄54．3岁。所有患者一侧行骨水泥型全膝关节置换，另一侧行非骨水泥型全膝关节置换，平均随访16．6年。结果发现，非骨水泥型与骨水泥型平均AKS评分分别是958分和969分，平均WOMAC骨关节炎指数分别是254和259，平均活动范围分别是125°和125°，平均满意度分别是81分和83分，且两组的放射学结果相似。因此作者认为，骨水泥型与非骨水泥型全膝关节置换治疗＜55岁的患者，效果都令人满意，无证据显示非骨水泥型全膝关节置换更具优势。