An Improved Signal Segmentation Using Moving Average and Savitzky-Golay Filter

Analysis of long-term EEG signals needs that it be segmented into pseudo stationary epochs. That work is done by regarding to statistical characteristics of a signal such as amplitude and frequency. Time series measured in real world is frequently non-stationary and to extract important information from the measured time series it is significant to utilize a filter or smoother as a pre-processing step. In the proposed approach, the signal is initially filtered by Moving Average (MA) or Savitzky-Golay filter to attenuate its short-term variations. Then, changes of the amplitude or frequency of the signal is calculated by Modified Varri method which is an acceptable algorithm for segmenting a signal. By using synthetic and real EEG data, the proposed methods are compared with original approach (simple Modified Varri). The simulation results indicate the absolute advantage of the proposed methods.

HYBRID REDUNDANCY APPROACH TO INCREASE THE RELIABILITY OF FPGA BASED SPEED CONTROLLER CORE FOR HIGH SPEED TRAIN

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger's safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy(HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security(RAMS) theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure(MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy(TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets(SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller.

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS

Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.