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High speed true random number generator with a new structure of coarse-tuning PDL in FPGA
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作者 Hongzhen Fang Pengjun Wang +1 位作者 Xu Cheng keji zhou 《Journal of Semiconductors》 EI CAS CSCD 2018年第3期60-65,共6页
A metastability-based TRNG(true random number generator) is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL(programmable delay line).With ... A metastability-based TRNG(true random number generator) is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL(programmable delay line).With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency,and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST(National Institute of Standards and Technology) and also accepted by class P1 of the AIS-20/31 test suite. 展开更多
关键词 TRNG FPGA metastability-based coarse-tuning PDL
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