Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell,sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms.A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell.Also,a sensing circuit of sense amplifier is proposed,based on D flip-flop structure to implement a simple sensing circuit.Furthermore,a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse.When an 8 bit eFuse OTP IP is designed with 0.18 μm standard CMOS logic of TSMC,the layout dimensions are 229.04 μm× 100.15 μm.All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

The direct current-direct current (DC-DC) converter is designed for 1 T static random access memory (SRAM) used in display driver integrated circuits (ICs), which consists of positive word-line voltage (VPWL), negative word-line voltage (VNWL) and half-VDD voltage (VHDD) generator. To generate a process voltage temperature (PVT)-insensitive VPWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VPWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VPWL regulator can provide a large driving current with a small area since it regulates an input voltage (VCI) from 2.5 to 3.3 V. The VNWL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.

Design of 256 bit single-poly MTP memory based on BCD process

We propose a single-poly MTP(multi-time programmable)cell consisting of one capacitor and two transistors based on MagnaChip's BCD process.The area of a unit cell is 37.743 75μm2.The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme.We design a 256 bit MTP memory for PMICs(power management ICs)using the proposed single-poly MTP cells.For small-area designs,we propose a selection circuit between V10V and V5V,and a WL(word-line)driver by simplifying its logic circuit.We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V(=10V)and V5V(=5V)without any additional charge pumps.The layout size of the designed 256 bit MTP memory is 618.250μm×437.425μm.

Stability of Semi-implicit Finite Volume Scheme for Level Set Like Equation

We study numerical methods for level set like equations arising in image processing and curve evolution problems. Semi-implicit finite volume-element type schemes are constructed for the general level set like equation （image selective smoothing model） given by Alvarez et al. （Alvarez L, Lions P L, Morel J M. Image selective smoothing and edge detection by nonlinear diffusion II. SIAM J. Numer. Anal., 1992, 29： 845-866）. Through the reasonable semi-implicit discretization in time and co-volume method for space approximation, we give finite volume schemes, unconditionally stable in L∞ and W1＇2 （W1＇1） sense in isotropic （anisotropic） diffu- sion domain.