A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity...A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.展开更多
针对有实时性需求的精简指令集计算机(Reduced Instruction Set Computer,RISC)-V处理器中断响应延迟过长的问题,本文改进了中断响应中中断服务程序跳转地址计算的方式,扩展了不可屏蔽中断(Non-Maskable Interrupt,NMI)响应时的控制寄存...针对有实时性需求的精简指令集计算机(Reduced Instruction Set Computer,RISC)-V处理器中断响应延迟过长的问题,本文改进了中断响应中中断服务程序跳转地址计算的方式,扩展了不可屏蔽中断(Non-Maskable Interrupt,NMI)响应时的控制寄存器,提出了硬件矢量中断以及NMI相关控制寄存器扩展。硬件矢量中断提高了中断的响应速度,减少了中断响应的延迟。NMI扩展控制寄存器减少了NMI的响应延迟,减少了软件需要进行的保存现场操作。利用VCS仿真验证了中断优化的正确性以及性能。仿真结果表明,硬件矢量中断响应时间缩短了84.4%,响应速度提高为原本的6倍,NMI扩展控制寄存器减少了31个时钟周期的响应时间以及32个时钟周期的返回时间。展开更多
针对国内对于专用通信引擎的研究空缺,实现了一种支持多协议的可配置通信引擎设计,并以典型的数据链路层协议——高级数据链路控制(High 1evel Data Link Control,HDLC)协议的引擎块实现为例,采用System Verilog搭建仿真平台,通过C语言...针对国内对于专用通信引擎的研究空缺,实现了一种支持多协议的可配置通信引擎设计,并以典型的数据链路层协议——高级数据链路控制(High 1evel Data Link Control,HDLC)协议的引擎块实现为例,采用System Verilog搭建仿真平台,通过C语言编写测试case,以回环验证的方式保证设计正确性。可配置引擎块以自研RSIC核为核心,采用AHB总线互连,内部集成HDLC、UART等通信协议以及DMA、TDM、GPIO等通用外设,实现通信协议的处理及数据传输,有助于解放处理器负载,提高数据处理效率,同时将HDLC与可配置通信引擎相结合,解决了多路信号的HDLC对处理器资源的占用率高等问题。展开更多
文摘A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.
文摘针对有实时性需求的精简指令集计算机(Reduced Instruction Set Computer,RISC)-V处理器中断响应延迟过长的问题,本文改进了中断响应中中断服务程序跳转地址计算的方式,扩展了不可屏蔽中断(Non-Maskable Interrupt,NMI)响应时的控制寄存器,提出了硬件矢量中断以及NMI相关控制寄存器扩展。硬件矢量中断提高了中断的响应速度,减少了中断响应的延迟。NMI扩展控制寄存器减少了NMI的响应延迟,减少了软件需要进行的保存现场操作。利用VCS仿真验证了中断优化的正确性以及性能。仿真结果表明,硬件矢量中断响应时间缩短了84.4%,响应速度提高为原本的6倍,NMI扩展控制寄存器减少了31个时钟周期的响应时间以及32个时钟周期的返回时间。
文摘针对国内对于专用通信引擎的研究空缺,实现了一种支持多协议的可配置通信引擎设计,并以典型的数据链路层协议——高级数据链路控制(High 1evel Data Link Control,HDLC)协议的引擎块实现为例,采用System Verilog搭建仿真平台,通过C语言编写测试case,以回环验证的方式保证设计正确性。可配置引擎块以自研RSIC核为核心,采用AHB总线互连,内部集成HDLC、UART等通信协议以及DMA、TDM、GPIO等通用外设,实现通信协议的处理及数据传输,有助于解放处理器负载,提高数据处理效率,同时将HDLC与可配置通信引擎相结合,解决了多路信号的HDLC对处理器资源的占用率高等问题。
