提出了一种基于单幅图像头部姿态估计的学生注意力可视化分析方法,采用随机级联回归树进行人脸特征点定位,引入了一个统计测量获得的刚性模型作为3D人脸近似,实现基于Pn P (perspective-n-point)映射的单幅图像头部姿态估计,最后将学生...提出了一种基于单幅图像头部姿态估计的学生注意力可视化分析方法,采用随机级联回归树进行人脸特征点定位,引入了一个统计测量获得的刚性模型作为3D人脸近似,实现基于Pn P (perspective-n-point)映射的单幅图像头部姿态估计,最后将学生视线投射到教师授课的视频图像上,实现学生学习注意力的可视化分析。实验结果表明:对于Biwi标准库,该方法可以将头部姿态估计角度平均误差降低到4.88°;方法具有粗颗粒度的计算并行性,使用4线程并行计算可以获得2.37倍的加速效果;实现了3种典型学习状态(专注、关注、漠视)的注意力可视化分析。展开更多
With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted...With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts： 1） An approach is proposed to delete all intermediate nodes of RL branches. 2） An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3） The Y to πtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground （P/G） networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.展开更多
文摘提出了一种基于单幅图像头部姿态估计的学生注意力可视化分析方法,采用随机级联回归树进行人脸特征点定位,引入了一个统计测量获得的刚性模型作为3D人脸近似,实现基于Pn P (perspective-n-point)映射的单幅图像头部姿态估计,最后将学生视线投射到教师授课的视频图像上,实现学生学习注意力的可视化分析。实验结果表明:对于Biwi标准库,该方法可以将头部姿态估计角度平均误差降低到4.88°;方法具有粗颗粒度的计算并行性,使用4线程并行计算可以获得2.37倍的加速效果;实现了3种典型学习状态(专注、关注、漠视)的注意力可视化分析。
基金supported by the National Natural Science Foundation of China(Grant No.60476014)the State"973"Key Basic Research Program(Grant No.2005CB321604)the UC Senate Research Fund.
文摘With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts： 1） An approach is proposed to delete all intermediate nodes of RL branches. 2） An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3） The Y to πtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground （P/G） networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.
