Multi-Rate SerDes Transceiver for IEEE 1394b Applications

This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.

A Phase Interpolator CDR with Low-Voltage CML Circuits

In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.

Novel Terpolymers of Poly(p-dioxanone-co-trimethylene carbonate-co-Lphenylalanine)： Synthesis, Characterization, Thermal Properties and Copolymerization Mechanism

In order to exploit the biological functions of materials, a series of new random terpolymers were synthesized by the ring-opening polymerization of p-dioxanone, trimethylene carbonate, and L-phenylalanine N-carboxyanhydride（L-PheNCA） in the presence of stannous octoate. The terpolymers were characterized by 1H-NMR, 13C-NMR, FTIR, and gel permeation chromatography. The effects of the reactant ratio, catalyst dosage, reaction temperature and time on the copolymerization were investigated, and were found to regulate the composition of the terpolymer. Increases in the reaction temperature, polymerization time, L-Phe-NCA monomer amount, and catalyst content generated a product with a slightly decreased molecular weight. The crystallinity of the terpolymer was investigated by differential scanning calorimetry and polarized optical microscopy. A reasonable mechanism for the polymerization was proposed based on the obtained results.