Current sustainability and electromigration of Pd,Sc and Y thin-films as potential interconnects

The progress on novel interconnects for carbon nanotube(CNT)-based electronic circuit is by far behind the remarkable development of CNT-field effect transistors.The Cu interconnect material used in current integrated circuits seems not applicable for the novel interconnects,as it requires electrochemical deposition followed by chemical-mechanical polishing.We report our experimental results on the failure current density,resistivity,electromigration effect and failure mechanism of patterned stripes of Pd,Sc and Y thin-films,regarding them as the potential novel interconnects.The Pd stripes have a failure current density of(8~10)×106 A/cm^2(MA/cm^2),and they are stable when the working current density is as much as 90% of the failure current density.However,they show a resistivity around 210 μΩ·cm,which is 20 times of the bulk value and leaving room for improvement.Compared to Pd,the Sc stripes have a similar resistivity but smaller failure current density of 4~5 MA/cm^2.Y stripes seem not suitable for interconnects by showing even lower failure current density than that of Sc and evidence of oxidation.For comparison,Au stripes of the same dimensions show a failure current density of 30 MA/cm^2 and a resistivity around 4 μΩ·cm,making them also a good material as novel interconnects.

One-dimensional perovskite-based Li-ion battery anodes with high capacity and cycling stability

Perovskite,widely used in solar cells,has also been proven to be potential candidate for effective energy storage material.Recent progress indicates the promise of perovskite for battery applications,however,the specific capacity of the resulting lithium-ion batteries must be further increased.Here,by adjusting the dimensionality of perovskite,we fabricated high-performing one-dimensional hybrid perovskite C_(4)H_(20)N_(4)PbBr_(6) based lithium-ion batteries,with the first specific capacity as high as 1632.8 mAh g^(-1)and a stable specific capacity of 598.0 mAh g^(-1)after 50 cycles under the condition of the constant current density of 150 mA g^(-1).The stable specific capacity is 2.36 times higher than that of the three-dimensional perovskite CH_(3)NH_(3)PbBr_(3)(253.2 mAh g^(-1)),and 1.6 times higher than that of the commercialized graphite electrode(372 mAh g^(-1)).The structure difference and the associated ion diffusivity are revealed to substantially affect the specific capacity of the perovskite-based lithium-ion battery.Our study opens up new directions for the applications of hybrid perovskites in energy storage devices.

Wafer-scale carbon-based CMOS PDK compatible with siliconbased VLSI design flow

Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.

Monolithic three-dimensional integration of aligned carbon nanotube transistors for high-performance integrated circuits

Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.

Sierpiński-triangle fractal crystals with the C_(3v)point group

Self-similar fractals are of importance in both science and engineering. Metal-organic Sierpin′ ski triangles are particularly attractive for applications in gas separation, catalysis and sensing. Such fractals are constructed in this study by using 1208 V-shaped 4,400-dicyano-1,10：30,100-terphenyl molecules and Fe atoms on Au（1 1 1）, and studied in detail by low-temperature scanning tunneling microscopy. Density functional theory calculations are employed to rationalize the invisible Fe atoms in STM images. Monte Carlo simulations are performed to understand the formation mechanism of the surface-supported fractal crystals.

Wafer-scale fabrication of carbon-nanotube-based CMOS transistors and circuits with high thermal stability

Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs.

Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor(CNT FET)has been considered as a promising candidate for future high-performance and low-power integrated circuits(ICs)applications owing to its ballistic transport and excellent immunity to short channel effects(SCEs).Still,it easily suffers from the ambipolar property,and severe leakage current at off-state originated from gate-induced drain leakage(GIDL)in CNT FETs with small bandgap.Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs,there is still a lack of the structure with excellent scalability,which will hamper the development of CNT FETs toward a competitive technology node.Here,we explore how the device geometry design affects the leakage current in CNT FETs,and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional(2D)TCAD simulations.Among all the proposed structures,the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process.According to the simulation results,the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/μm and an on-current as high as about 2.1 mA/μm at a supply voltage of-1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

Flexible Integrated Circuits Based on Carbon Nanotubes

CONSPECTUS:Flexible integrated circuits,working as the core unit of information processing,have been a subject of extensive research;they are essential to realize fully flexible electronic systems,which possess advantages over the current hybrid flexible systems(part or all based on rigid silicon chips)because of their extended application forms,better adaptability,and greater ability to operate at biotic/abiotic interfaces.To a great extent,the deliverable functionality of the ultimate integrated system is determined by the information handling capability of flexible integrated circuits,which is highly dependent on their performance and integration scale.Additionally,as the applications of flexible electronic systems become increasingly favorable in portable,wearable,or remote forms with a restrained power supply,the power dissipation of flexible integrated circuits becomes crucial,as they consume considerable energy in a system.Due to the restricted fabrication circumstances on flexible substrates with a low thermal budget and complex working environments(from the perspectives of both mechanical and electrical conditions),pursuing flexible integrated circuits with high performance,decent integration scale,and low power consumption is very challenging,but it is necessary for advanced,fully flexible systems.Other characteristics,such as biocompatibility,degradability,and configurability,would add value to flexible integrated circuits and introduce unconventional forms and new deliverables for flexible electronics.In this Account,we summarize our efforts toward developing carbon nanotube-based flexible integrated circuits over the past five years.As promising candidates for constructing next-generation chips,carbon nanotube-based integrated circuits have demonstrated their superiority in performance and power consumption,and we extend these advancements to a flexible form through material optimization,device design,processing technology development,etc.We start with a brief introduction to carbon nanotube properties to reveal their intrinsic advantages as channel materials for next-generation electronics.Next,we discuss the manufacturing methods we developed to construct integrated circuits on flexible substrates via a direct fabrication or transfer process to maintain these advantages and fit the circuits to different application circumstances.Then,demonstrations of carbon nanotubebased flexible integrated circuits with different forms and characteristics are presented,including(1)the implantation of complementary metal-oxide-semiconductor circuits on ultrathin substrates with high performance,(2)transferrable integrated circuits with a biointegration capability and low power consumption,(3)degradable integrated circuits manufactured at the wafer scale with a high yield and high uniformity,and(4)configurable integrated circuits with multiple functions.Integrated flexible sensor systems constructed with some of these circuits have also been introduced.Finally,we end the Account with an overview of the remaining challenges and new opportunities that have been opened up for carbon nanotubes in flexible integrated circuits and new forms of electronics.

Carbon nanotube network film-based ring oscillators with sub l O-ns propagation time and their applications in radio-frequency signal transmission

We have fabricated top-gated ambipolar field-effect transistors （FETs） based on solution-derived carbon nanotube （CNT） network films, and then constructed inverters and ring oscillators （ROs） that can work under supply voltages as low as 0.2 V owing to the high uniformity of the devices. Significant improvements were achieved in the performance of these CNT-based ambipolar FETs and CMOS-like circuits by scaling down the gate length of the CNT FETs and optimizing the device structure and RO layout. In particular, the optimized five-stage RO is shown to present a record high oscillation frequency of up to 17.4 MHz with a propagation time of 5.6 ns at a 12-V working voltage. The CNT film-based ROs were used as carrier-wave generators in radio-frequency systems to demonstrate a complete signal transmission process. These results suggest that CNT thin film-based FETs and integrated circuits may soon find their way to radio-frequency applications with a frequency band of 13.56 MHz.

How to build good inverters from nanomaterial-based transistors

As promising components of future integrated circuits(ICs),field-effect transistors(FETs)based on semiconducting nanomaterials are being extensively investigated.As the most essential component of ICs,inverters are favored to be demonstrated at the infant stage of emerging technologies.However,systematic research is absent to reveal how the parameters of transistors affect the performance of inverters,e.g.the voltage transfer characteristics(VTCs).In this work,systematic analysis about the dependency between transistor-and inverter-level metrics have been carried out for both complementary metal-oxide-semiconductor(CMOS)and monotype(p-type-only and n-type-only)technologies,which is further experimentally demonstrated by carbon nanotube FETs and ICs.We also propose guidelines towards the high noise margin and rail-to-rail inverter design based on nanomaterials.

Recent progress of photodetector based on carbon nanotube film and application in optoelectronic integration

Due to its remarkable electrical and optical capabilities,optoelectronic devices based on the semiconducting single-walled carbon nanotube(s-SWCNT)have been studied extensively in the last two decades.First,s-SWCNT is a direct bandgap semiconductor with a high infrared absorption coefficient and high electron/hole mobility.In addition,as a typical one-dimensional material,there is no lattice mismatch between s-SWCNT and any substrates.Another advantage is that the optoelectronic devices of s-SWCNT can be processed at low temperatures.s-SWCNT has intriguing potential and applications in solar cells,light-emitting diodes(LEDs),photodetectors,and three-dimensional(3D)optoelectronic integration.In recent years,along with the advancement of solution purification technology,the high-purity s-SWCNTs film has laid the foundation for constructing large-area,homogenous,and high-performance optoelectronic devices.In this review,optoelectronic devices based on s-SWCNTs film and related topics are reviewed,including the preparation of high purity s-SWCNTs film,the progress of photodetectors based on the s-SWCNTs film,and challenges of s-SWCNTs film photodetectors.