An Enhanced Energy Efficiency Tree-Based Hierarchical Routing Based on Additional Connections

Instrumented is defined as a key characteristic in the upcoming smart cites, which demands a higher Wireless Sensor Networks (WSNs) performance. Tree-based Hierarchical Routing (THR) is a routing protocol for WSNs static scenarios. THR hierarchically maps WSN area into a routing tree. However, fixed topology and hierarchical architecture leads to unbalanced energy overhead distribution and inflexible routes selection. To uniformly distribute routing energy overhead, reduce routing hops and extend network life cycle, we designed an enhanced THR routing protocol based on additional connections such as Neighbors, Brothers and Nephews. Based on these connections, three actions were introduced which are Shortcut, Overhead Balancing and Adoption. A simulation for different network loads on OMNet++4.1 is issued, and realized this THR routing in Chipcon SmartRF04?EB embedded boards based on Zigbee in a point-to-point topology. According to the simulation results and experiment data, this proposal obviously improved the latency performance, reduced energy overhead and extended the network’s life cycle.

MilkyWay-2 supercomputer： system and application

On June 17, 2013, MilkyWay-2 （Tianhe-2） supercomputer was crowned as the fastest supercomputer in the world on the 41th TOP500 list. This paper provides an overview of the MilkyWay-2 project and describes the design of hardware and software systems. The key architecture features of MilkyWay-2 are highlighted, including neo-heterogeneous compute nodes integrating commodity- off-the-shelf processors and accelerators that share similar instruction set architecture, powerful networks that employ proprietary interconnection chips to support the massively parallel message-passing communications, proprietary 16- core processor designed for scientific computing, efficient software stacks that provide high performance file system, emerging programming model for heterogeneous systems, and intelligent system administration. We perform extensive evaluation with wide-ranging applications from LINPACK and Graph500 benchmarks to massively parallel software deployed in the system.

Pinpointing and scheduling access conflicts to improve internal resource utilization in solid-state drives

Modern solid-state drives (SSDs)are integrating more internal resources to achieve higher capacity.Parallelizing accesses across internal resources can potentially enhance the performance of SSDs.However,exploiting parallelism inside SSDs is challenging owing to real-time access conflicts.In this paper,we propose a highly parallelizable I/O scheduler (PIOS)to improve internal resource utilization in SSDs from the perspective of I/O scheduling.Specifically, we first pinpoint the conflicting flash requests with precision during the address translation in the Flash Translation Layer (FTL).Then,we introduce conflict eliminated requests (CERs)to reorganize the I/O requests in the device-level queue by dispatching conflicting flash requests to different CERs.Owing to the significant performance discrepancy between flash read and write operations,PIOS employs differentiated scheduling schemes for read and write CER queues to always allocate internal resources to the conflicting CERs that are more valuable.The small dominant size prioritized scheduling policy for the write queue significantly decreases the average write latency.The high parallelism density prioritized scheduling policy for the read queue better utilizes resources by exploiting internal parallelism aggressively.Our evaluation results show that the paralle/izable I/O scheduler (PIOS)can accomplish better SSD performance than existing I/O schedulers implemented in both SSD devices and operating systems.