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Messages from CEISEE 2023 Committee
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作者 Xiaofei Xu Bing Wu +9 位作者 Bing Li luciano baresi Wei Lu Rong Peng Yves Ducq Jifeng Xuan Cindy Liu Weiwei Xing Xiaoyuan Xie Peng Liang 《计算机教育》 2023年第12期1-1,共1页
The China-Europe International Symposium on Software Engineering Education(CEISEE)is an international educational conference jointly initiated by Harbin Institute of Technology and Technological University Dublin in 2... The China-Europe International Symposium on Software Engineering Education(CEISEE)is an international educational conference jointly initiated by Harbin Institute of Technology and Technological University Dublin in 2005.The CEISEE is held alternately in China and Europe every year.The host cities include Harbin,Dublin in Ireland,Guangzhou,Bordeaux in France,Xi’an,Northampton in the United Kingdom,Shanghai,Milan in Italy,Chengdu,Zwikau in Germany,Shenyang,Athens in Greece,Shenzhen,Lisbon in Portugal,Beijing,and Wuhan in 2023.The conference has been gaining increasing international influence. 展开更多
关键词 DUBLIN jointly initiated
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Towards a Formal Semantics for UML/MARTE State Machines Based on Hierarchical Timed Automata 被引量:7
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作者 Yu Zhou luciano baresi Matteo Rossi 《Journal of Computer Science & Technology》 SCIE EI CSCD 2013年第1期188-202,共15页
UML is a widely-used, general purpose modeling language. But its lack of a rigorous semantics forbids the thorough analysis of designed solution, and thus precludes the discovery of significant problems at design time... UML is a widely-used, general purpose modeling language. But its lack of a rigorous semantics forbids the thorough analysis of designed solution, and thus precludes the discovery of significant problems at design time. To bridge the gap, the paper investigates the underlying semantics of UML state machine diagrams, along with the time-related modeling elements of MARTE, the profile for modeling and analysis of real-time embedded systems, and proposes a formal operational semantics based on extended hierarchical timed automata. The approach is exemplified on a simple example taken from the automotive domain. Verification is accomplished by translating designed models into the input language of the UPPAAL model checker. 展开更多
关键词 timed automata state machine diagram formal semantics
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