Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.

An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling

We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor(MOSFET) in the linear and saturation regions for fast analytical calculation of the current.The model is based on the BSIM3v3 model.Instead of using constant threshold voltage and early voltage,as is assumed in the BSIM3v3 model,we define these voltages as functions of the gate-source voltage.The accuracy of the model is verified by comparison with HSPICE for the 90-,65-,45-,and 32-nm CMOS technologies.The model shows better accuracy than the nth-power and BSIM3v3 models.Then,we use the proposed I-V model to calculate the read static noise margin(SNM) of nano-scale conventional 6T static random-access memory(SRAM) cells with high accuracy.We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed.The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-,65-,45-,and 32-nm technologies.Verification in the presence of process variations and negative bias temperature instability(NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.