The single-walled carbon nanotube （SWCNT） is a promising nanostructure in the design of future high- frequency system-on-chip, especially in network-on-chip, where the quality of communication between intellectual p...The single-walled carbon nanotube （SWCNT） is a promising nanostructure in the design of future high- frequency system-on-chip, especially in network-on-chip, where the quality of communication between intellectual property （IP） modules is a major concern. Shrinking dimensions of circuits and systems have restricted the use of high-frequency signal characteristics for frequencies up to 1000 GHz. Four key electrical parameters, impedance, propagation constant, current density, and signal delay time, which are crucial in the design of a high-quality interconnect, are derived for different structural configurations of SWCNT. Each of these parameters exhibits strong dependence on the frequency range over which the interconnect is designed to operate, as well as on the configuration of SWCNT. The novelty of the proposed model for solving next-generation high-speed integrated circuit （IC） interconnect challenges is illustrated, compared with existing theoretical and experimental results in the literature.展开更多
文摘The single-walled carbon nanotube （SWCNT） is a promising nanostructure in the design of future high- frequency system-on-chip, especially in network-on-chip, where the quality of communication between intellectual property （IP） modules is a major concern. Shrinking dimensions of circuits and systems have restricted the use of high-frequency signal characteristics for frequencies up to 1000 GHz. Four key electrical parameters, impedance, propagation constant, current density, and signal delay time, which are crucial in the design of a high-quality interconnect, are derived for different structural configurations of SWCNT. Each of these parameters exhibits strong dependence on the frequency range over which the interconnect is designed to operate, as well as on the configuration of SWCNT. The novelty of the proposed model for solving next-generation high-speed integrated circuit （IC） interconnect challenges is illustrated, compared with existing theoretical and experimental results in the literature.
