An Efficient Reference Free Adaptive Learning Process for Speech Enhancement Applications

In issues like hearing impairment,speech therapy and hearing aids play a major role in reducing the impairment.Removal of noise signals from speech signals is a key task in hearing aids as well as in speech therapy.During the transmission of speech signals,several noise components contaminate the actual speech components.This paper addresses a new adaptive speech enhancement(ASE)method based on a modified version of singular spectrum analysis(MSSA).The MSSA generates a reference signal for ASE and makes the ASE is free from feeding reference component.The MSSA adopts three key steps for generating the reference from the contaminated speech only.These are decomposition,grouping and reconstruction.The generated reference is taken as a reference for variable size adaptive learning algorithms.In this work two categories of adaptive learning algorithms are used.They are step variable adaptive learning(SVAL)algorithm and time variable step size adaptive learning(TVAL).Further,sign regressor function is applied to adaptive learning algorithms to reduce the computational complexity of the proposed adaptive learning algorithms.The performance measures of the proposed schemes are calculated in terms of signal to noise ratio improvement(SNRI),excess mean square error(EMSE)and misadjustment(MSD).For cockpit noise these measures are found to be 29.2850,-27.6060 and 0.0758 dB respectively during the experiments using SVAL algorithm.By considering the reduced number of multiplications the sign regressor version of SVAL based ASE method is found to better then the counter parts.

Design of Low Power Transmission Gate Based 9T SRAM Cell

Considerable research has considered the design of low-power and high-speed devices.Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices.Embedded static random-access memory(SRAM)units are necessary components in fast mobile computing.Traditional SRAM cells are more energyconsuming and with lower performances.The major constraints in SRAM cells are their reliability and low power.The objectives of the proposed method are to provide a high read stability,low energy consumption,and better writing abilities.A transmission gate-based multi-threshold single-ended Schmitt trigger(ST)9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed.Herein,an ST inverter with a single bit-line design is used to attain the high read stability.A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter.The multithreshold complementary metal oxide semiconductor(MTCMOS)technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM cell.The proposed system uses a combination of standard and ST inverters,which results in a large read stability.Compared with the previous ST 9T,ST 11T,11T,10T,and 7T SRAM cells,the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%,42.09%,31.60%,12.54%,and 31.60%less energy for read operations and 73.59%,93.95%,92.76%,89.23%,and 85.78%less energy for write operations,respectively.