There is a continuous demand to reduce the size of the devices that form a unit circuit,such as logic gates and memory,to reduce their footprint and increase device integration.In order to achieve a highly efficient c...There is a continuous demand to reduce the size of the devices that form a unit circuit,such as logic gates and memory,to reduce their footprint and increase device integration.In order to achieve a highly efficient circuit architecture,optimizations need to be made in terms of device processing.However,the time involved in the current reduction of device sizes according to Moore's Law has slowed down.Here,we propose a flexible transistor with ultra-thin IGZO(InGaZnO,indium-gallium-zinc-oxide)as the channel material,which not only scales down the footprints of multi-transistor logic gates but also combines the functions of the logic gates,memory,and sensors into a single cell.The transistor proposed here has an ultrathin semiconductor layer and can implement the typical functions of logic gates that conventionally have 2-6 transistors.Furthermore,it demonstrates the memory effect with a programming time as low as 5 ns.This design can also display various artificial synaptic behaviors.This new device design and structure can be adopted for the development of next-generation flexible electronics that require higher integration.展开更多
The article "Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint" written by Chaoqi Dai,Peiqin Chen,Shaocheng Qi,Yongbin Hu,Zhitang Song,and Mingzhi ...The article "Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint" written by Chaoqi Dai,Peiqin Chen,Shaocheng Qi,Yongbin Hu,Zhitang Song,and Mingzhi Dai,was erroneously originally published electronically on the publisher’internet portal(currently SpringerLink)on 30 September 2020 with caption of Fig.1 and related context,and the Acknowledgements.展开更多
The feature information of the local graph structure and the nodes may be over-smoothing due to the large number of encodings,which causes the node characterization to converge to one or several values.In other words,...The feature information of the local graph structure and the nodes may be over-smoothing due to the large number of encodings,which causes the node characterization to converge to one or several values.In other words,nodes from different clusters become difficult to distinguish,as two different classes of nodes with closer topological distance are more likely to belong to the same class and vice versa.To alleviate this problem,an over-smoothing algorithm is proposed,and a method of reweighted mechanism is applied to make the tradeoff of the information representation of nodes and neighborhoods more reasonable.By improving several propagation models,including Chebyshev polynomial kernel model and Laplace linear 1st Chebyshev kernel model,a new model named RWGCN based on different propagation kernels was proposed logically.The experiments show that satisfactory results are achieved on the semi-supervised classification task of graph type data.展开更多
基金the National Natural Science Foundation of China(No.61574147)Zhejiang Provincial Natural Science Foundation for Distinguished Young Scholar(No.LR17F040002)+1 种基金Ningbo Natural Science Foundation of China(No.2018A610003)Instrument Developing Project of the Chinese Academy of Sciences(No.YJKYYQ20180021).We would like to thank Editage(www.editage.com)for their English language and editing support.
文摘There is a continuous demand to reduce the size of the devices that form a unit circuit,such as logic gates and memory,to reduce their footprint and increase device integration.In order to achieve a highly efficient circuit architecture,optimizations need to be made in terms of device processing.However,the time involved in the current reduction of device sizes according to Moore's Law has slowed down.Here,we propose a flexible transistor with ultra-thin IGZO(InGaZnO,indium-gallium-zinc-oxide)as the channel material,which not only scales down the footprints of multi-transistor logic gates but also combines the functions of the logic gates,memory,and sensors into a single cell.The transistor proposed here has an ultrathin semiconductor layer and can implement the typical functions of logic gates that conventionally have 2-6 transistors.Furthermore,it demonstrates the memory effect with a programming time as low as 5 ns.This design can also display various artificial synaptic behaviors.This new device design and structure can be adopted for the development of next-generation flexible electronics that require higher integration.
文摘The article "Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint" written by Chaoqi Dai,Peiqin Chen,Shaocheng Qi,Yongbin Hu,Zhitang Song,and Mingzhi Dai,was erroneously originally published electronically on the publisher’internet portal(currently SpringerLink)on 30 September 2020 with caption of Fig.1 and related context,and the Acknowledgements.
文摘The feature information of the local graph structure and the nodes may be over-smoothing due to the large number of encodings,which causes the node characterization to converge to one or several values.In other words,nodes from different clusters become difficult to distinguish,as two different classes of nodes with closer topological distance are more likely to belong to the same class and vice versa.To alleviate this problem,an over-smoothing algorithm is proposed,and a method of reweighted mechanism is applied to make the tradeoff of the information representation of nodes and neighborhoods more reasonable.By improving several propagation models,including Chebyshev polynomial kernel model and Laplace linear 1st Chebyshev kernel model,a new model named RWGCN based on different propagation kernels was proposed logically.The experiments show that satisfactory results are achieved on the semi-supervised classification task of graph type data.
