Thermally annealed gamma irradiated Ni/4H-SiC Schottky barrier diode characteristics

Thermal annealing effects on gamma irradiated Ni/4 H-SiC Schottky barrier diode(SBD) characteristics are analyzed over a wide range of temperatures(400–1100 °C). The annealing induced variations in the concentration of deep level traps in the SBDs are identified by thermally stimulated capacitance(TSCAP). A little decrease in the trap density at E_C – 0.63 eV and E_C –1.13 eV is observed up to the annealing temperature of 600 °C. Whereas, a gamma induced trap at E_C – 0.89 eV disappeared after annealing at 500 °C, revealing that its concentration(< 1013 cm-3) is reduced below the detection limit of the TSCAP technique.The electrical characteristics of irradiated SBDs are considerably changed at each annealing temperature. To understand the anomalous variations in the post-annealing characteristics, the interface state density distribution in the annealed SBDs is extracted.The electrical properties are improved at 400 °C due to the reduction in the interface trap density. However, from 500 °C, the electrical parameters are found to degrade with the annealing temperature because of the increase in the interface trap density.From the results, it is noted that the rectifying nature of the SBDs vanishes at or above 800 °C.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current–voltage（I–V） characteristics of the 4H-SiC metal semiconductor field effect transistor（MESFET） on a high purity semi-insulating（HPSI） substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation.The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations（Silvaco -TCAD）. The proposed model also illustrates the effectiveness of the gate–source distance scaling effect compared to the gate–drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits（MMICs） on HPSI substrates.