Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits

Carbon nanotube field-effect transistors(CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing(AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input(GDI) technique are merged, and three new AC-based full adders(FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II(NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by about 50% in terms of power-delay-product(PDP) at the cost of area occupation. The Monte Carlo method(MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold(DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit(LSB) parts of more complex arithmetic circuits such as multipliers.

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

We present a new counter-based Wallace-tree(CBW)8×8 multiplier.The multiplier’s counters are implemented with a new hybrid full adder(FA)cell,which is based on the transmission gate(TG)technique.The proposed FA,TG-based AND gate,and hybrid half adder(HA)generate M:3(4≤M≤7)digital counters with the ability to save at least 50%area occupation.Simulations by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art designs.By using the proposed cells,the CBW multiplier exhibits high driving capability,low power consumption,and high speed.The CBW multiplier has a 0.0147 mm^(2)die area in a pad.The post-layout extraction proves the accuracy of experimental implementation.An image blending mechanism is proposed,in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing applications.The peak signal-to-noise ratio(PSNR)and structural similarity index metric(SSIM)are calculated as image quality parameters,and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.