In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quant...In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.展开更多
This study focused on the determination and analysis of an accurate analytical model for PIN diode under different bias conditions. This approach employs analytically derived expressions including the variation of the...This study focused on the determination and analysis of an accurate analytical model for PIN diode under different bias conditions. This approach employs analytically derived expressions including the variation of the depletion regions in the device to make the used model available over a wide range of testing conditions without remake the parameters extraction procedure. The validity of the proposed extraction procedure has been verified by the very good agreement between simulated and measured current and voltage waveforms reverse recovery at different range of the operation conditions. The model is developed and simulated with the VHDL-AMS language under Ansoft Simplorer®Environment.展开更多
In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication st...In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.展开更多
文摘In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.
文摘This study focused on the determination and analysis of an accurate analytical model for PIN diode under different bias conditions. This approach employs analytically derived expressions including the variation of the depletion regions in the device to make the used model available over a wide range of testing conditions without remake the parameters extraction procedure. The validity of the proposed extraction procedure has been verified by the very good agreement between simulated and measured current and voltage waveforms reverse recovery at different range of the operation conditions. The model is developed and simulated with the VHDL-AMS language under Ansoft Simplorer®Environment.
文摘In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.
