Markov chains are extensively used in modeling different aspects of engineering and scientific systems, such as performance of algorithms and reliability of systems. Different techniques have been developed for analyz...Markov chains are extensively used in modeling different aspects of engineering and scientific systems, such as performance of algorithms and reliability of systems. Different techniques have been developed for analyzing Markovian models, for example, Markov Chain Monte Carlo based simulation, Markov Analyzer, and more recently probabilistic model- checking. However, these techniques either do not guarantee accurate analysis or are not scalable. Higher-order-logic theorem proving is a formal method that has the ability to overcome the above mentioned limitations. However, it is not mature enough to handle all sorts of Markovian models. In this paper, we propose a formalization of Discrete-Time Markov Chain （DTMC） that facilitates formal reasoning about time-homogeneous finite-state discrete-time Markov chain. In particular, we provide a formal verification on some of its important properties, such as joint probabilities, Chapman-Kolmogorov equation, reversibility property, using higher-order logic. To demonstrate the usefulness of our work, we analyze two applications： a simplified binary communication channel and the Automatic Mail Quality Measurement protocol.展开更多
Probabilistic techniques are widely used in the analysis of algorithms to estimate the computational complexity of algorithms or a computational problem.Traditionally,such analyses are performed using paper-and-pencil...Probabilistic techniques are widely used in the analysis of algorithms to estimate the computational complexity of algorithms or a computational problem.Traditionally,such analyses are performed using paper-and-pencil proofs and the results are sometimes validated using simulation techniques.These techniques are informal and thus may result in an inaccurate analysis.In this paper,we propose a formal technique for analyzing the expected time complexity of algorithms using higher-order-logic theorem proving.The approach calls for mathematically modeling the algorithm along with its inputs,using indicator random variables,in higher-order logic.This model is then used to formally reason about the expected time complexity of the underlying algorithm in a theorem prover.The paper includes the higher-order-logic formalization of indicator random variables,which are fundamental to the proposed infrastructure.In order to illustrate the practical effiectiveness and utilization of the proposed infrastructure,the paper also includes the analysis of algorithms for three well-known problems,i.e.,the hat-check problem,the birthday paradox and the hiring problem.展开更多
文摘Markov chains are extensively used in modeling different aspects of engineering and scientific systems, such as performance of algorithms and reliability of systems. Different techniques have been developed for analyzing Markovian models, for example, Markov Chain Monte Carlo based simulation, Markov Analyzer, and more recently probabilistic model- checking. However, these techniques either do not guarantee accurate analysis or are not scalable. Higher-order-logic theorem proving is a formal method that has the ability to overcome the above mentioned limitations. However, it is not mature enough to handle all sorts of Markovian models. In this paper, we propose a formalization of Discrete-Time Markov Chain （DTMC） that facilitates formal reasoning about time-homogeneous finite-state discrete-time Markov chain. In particular, we provide a formal verification on some of its important properties, such as joint probabilities, Chapman-Kolmogorov equation, reversibility property, using higher-order logic. To demonstrate the usefulness of our work, we analyze two applications： a simplified binary communication channel and the Automatic Mail Quality Measurement protocol.
文摘Probabilistic techniques are widely used in the analysis of algorithms to estimate the computational complexity of algorithms or a computational problem.Traditionally,such analyses are performed using paper-and-pencil proofs and the results are sometimes validated using simulation techniques.These techniques are informal and thus may result in an inaccurate analysis.In this paper,we propose a formal technique for analyzing the expected time complexity of algorithms using higher-order-logic theorem proving.The approach calls for mathematically modeling the algorithm along with its inputs,using indicator random variables,in higher-order logic.This model is then used to formally reason about the expected time complexity of the underlying algorithm in a theorem prover.The paper includes the higher-order-logic formalization of indicator random variables,which are fundamental to the proposed infrastructure.In order to illustrate the practical effiectiveness and utilization of the proposed infrastructure,the paper also includes the analysis of algorithms for three well-known problems,i.e.,the hat-check problem,the birthday paradox and the hiring problem.
