In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC ...In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.展开更多
We propose a high performance 10-bit 100-MS/s(million samples per second)successive approximation register(SAR)analog-to-digital converter(ADC)with mismatch correction latch and improved comparator clock.Using a high-...We propose a high performance 10-bit 100-MS/s(million samples per second)successive approximation register(SAR)analog-to-digital converter(ADC)with mismatch correction latch and improved comparator clock.Using a high-low supply voltage technology,the bias output impedance of the preamplifier of the comparator is increased.Therefore,the common mode rejection ratio(CMRR)of the comparator is improved,and further diminishing the signal-dependent offset caused by the input common-mode voltage variation.A digital-to-analog converter(DAC)control signal correction latch is proposed to correct the control signal error resulted from process mismatch.The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free dynamic range(SFDR)of the ADC is improved by 2 dB with this correction latch.To ensure sufficient high bit switching time of the DAC and sufficient low bit comparison time of the comparator,a data selector used in the comparator clock is presented.The optimized time distribution improves the performance of the SAR ADC.This prototype was fabricated using a one-poly-eight-metal(1 P8 M)55 nm complementary metal oxide semiconductor(CMOS)technology.With measured results at 1.3 V/1.5 V supply and 100-MS/s,the ADC achieves a signalto-noise and distortion ratio(SNDR)of 59.4 dB and consumes 2.1 mW,resulting in a figure of merit(FOM)of31 fJ/conversion-step.In addition,the active area of the ADC is 0.018 8 mm2.展开更多
文摘In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.
基金the National Science and Technology Major Project(No.2014ZX03001011)the National Natural Science Foundation of China(No.61704143)the Natural Science Foundation of Fujian Province(No.2018J01566)
文摘We propose a high performance 10-bit 100-MS/s(million samples per second)successive approximation register(SAR)analog-to-digital converter(ADC)with mismatch correction latch and improved comparator clock.Using a high-low supply voltage technology,the bias output impedance of the preamplifier of the comparator is increased.Therefore,the common mode rejection ratio(CMRR)of the comparator is improved,and further diminishing the signal-dependent offset caused by the input common-mode voltage variation.A digital-to-analog converter(DAC)control signal correction latch is proposed to correct the control signal error resulted from process mismatch.The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free dynamic range(SFDR)of the ADC is improved by 2 dB with this correction latch.To ensure sufficient high bit switching time of the DAC and sufficient low bit comparison time of the comparator,a data selector used in the comparator clock is presented.The optimized time distribution improves the performance of the SAR ADC.This prototype was fabricated using a one-poly-eight-metal(1 P8 M)55 nm complementary metal oxide semiconductor(CMOS)technology.With measured results at 1.3 V/1.5 V supply and 100-MS/s,the ADC achieves a signalto-noise and distortion ratio(SNDR)of 59.4 dB and consumes 2.1 mW,resulting in a figure of merit(FOM)of31 fJ/conversion-step.In addition,the active area of the ADC is 0.018 8 mm2.
