With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of...With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram （BDD）. First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.展开更多
随着电动汽车的发展,轴向磁通电机(Axial Field Flux-Switching Permanent Magnet,AFFSPM)因其高比功率和高转矩密度的优点,受到广大汽车主机厂的认可。针对AFFSPM控制现状进行介绍,包括基于AFFSPM数学模型的控制方法和非AFFSPM数学模...随着电动汽车的发展,轴向磁通电机(Axial Field Flux-Switching Permanent Magnet,AFFSPM)因其高比功率和高转矩密度的优点,受到广大汽车主机厂的认可。针对AFFSPM控制现状进行介绍,包括基于AFFSPM数学模型的控制方法和非AFFSPM数学模型控制方法2大类,并对每类控制方法中具体内容进行详细阐述,为AFFSPM控制的应用场合提供参考。展开更多
The main task of system reliability design is to find the best layout of components to maximize reliability or to minimize cost. A reliability optimization approach using neural networks to identify the choice of comp...The main task of system reliability design is to find the best layout of components to maximize reliability or to minimize cost. A reliability optimization approach using neural networks to identify the choice of components in series-parallel systems with multiple constraints is presented in this paper. The McCullochPittes neural network model is used in this approach. The design methods of the neural network construction and its energy function are described in detail. The optimal solutions of the reliability problem are obtained by minimizing the energy function of the neural networks. Simulation results show the reliability optimization approach using neural networks can find the optimal or near-optimal solutions for most of the problems in a relatively short time, it is a useful alternative for system reliability design of complex systems.展开更多
The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set...The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.展开更多
The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circ...The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.展开更多
As the complexity of nanocircuits continues to increase,developing tests for them becomes more difficult.Failure analysis and the localization of internal test points within nanocircuits are already more difficult tha...As the complexity of nanocircuits continues to increase,developing tests for them becomes more difficult.Failure analysis and the localization of internal test points within nanocircuits are already more difficult than for conventional integrated circuits.In this paper,a new method of testing for faults in nanocircuits is presented that uses single-photon detection to locate failed components(or failed signal lines)by utilizing the infrared photon emission characteristics of circuits.The emitted photons,which can carry information about circuit structure,can aid the understanding of circuit properties and locating faults.In this paper,in order to enhance the strength of emitted photons from circuit components,test vectors are designed for circuits’components or signal lines.These test vectors can cause components to produce signal transitions or switching behaviors according to their positions,thereby increasing the strength of the emitted photons.A multiple-valued decision diagram(MDD),in the form of a directed acrylic graph,is used to produce the test vectors.After an MDD corresponding to a circuit is constructed,the test vectors are generated by searching for specific paths in the MDD of that circuit.Experimental results show that many types of faults such as stuck-at faults,bridging faults,crosstalk faults,and others,can be detected with this method.展开更多
The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The t...The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.展开更多
基金Supported by the National Natural Science Foun-dation of China (60006002) Natural Science Research Project of Education Department of Guangdong Province of China (02019)
文摘With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram （BDD）. First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.
文摘随着电动汽车的发展,轴向磁通电机(Axial Field Flux-Switching Permanent Magnet,AFFSPM)因其高比功率和高转矩密度的优点,受到广大汽车主机厂的认可。针对AFFSPM控制现状进行介绍,包括基于AFFSPM数学模型的控制方法和非AFFSPM数学模型控制方法2大类,并对每类控制方法中具体内容进行详细阐述,为AFFSPM控制的应用场合提供参考。
基金Supported by the National Natural Science Foundation of China (60006002) and Natural Science Research Project of Education Depart-ment of Guangdong Province of China (02019)
文摘The main task of system reliability design is to find the best layout of components to maximize reliability or to minimize cost. A reliability optimization approach using neural networks to identify the choice of components in series-parallel systems with multiple constraints is presented in this paper. The McCullochPittes neural network model is used in this approach. The design methods of the neural network construction and its energy function are described in detail. The optimal solutions of the reliability problem are obtained by minimizing the energy function of the neural networks. Simulation results show the reliability optimization approach using neural networks can find the optimal or near-optimal solutions for most of the problems in a relatively short time, it is a useful alternative for system reliability design of complex systems.
基金Supported by the National Natural Science Foundation of China (No.60006002)the Education Department of Guangdong Province of China (No.02019).
文摘The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.
基金Supported by the National Natural Science Foundation of China (No.60006002)the Education Department of Guangdong Province of China (No.02019).
文摘The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.
基金supported by the National Natural Science Foundation of China(Grant No.61072028)the Project of the Department of Education of Guangdong Province(Grant No.2012KJCX0040)the Guangdong Province and Chinese Ministry of Education Cooperation Project of Industry,Education,and Academy(Grant No.2009B090300339)
文摘As the complexity of nanocircuits continues to increase,developing tests for them becomes more difficult.Failure analysis and the localization of internal test points within nanocircuits are already more difficult than for conventional integrated circuits.In this paper,a new method of testing for faults in nanocircuits is presented that uses single-photon detection to locate failed components(or failed signal lines)by utilizing the infrared photon emission characteristics of circuits.The emitted photons,which can carry information about circuit structure,can aid the understanding of circuit properties and locating faults.In this paper,in order to enhance the strength of emitted photons from circuit components,test vectors are designed for circuits’components or signal lines.These test vectors can cause components to produce signal transitions or switching behaviors according to their positions,thereby increasing the strength of the emitted photons.A multiple-valued decision diagram(MDD),in the form of a directed acrylic graph,is used to produce the test vectors.After an MDD corresponding to a circuit is constructed,the test vectors are generated by searching for specific paths in the MDD of that circuit.Experimental results show that many types of faults such as stuck-at faults,bridging faults,crosstalk faults,and others,can be detected with this method.
基金Supported by the Guangdong Provincial Natural Science Foundation of China(2014A030313441)the Guangzhou Science and Technology Project(201510010169)+1 种基金the Guangdong Province Science and Technology Project(2016B090918071,2014A040401076)the National Natural Science Foundation of China(61072028)
文摘The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.
