Network-on-chip(NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip(SoC) designs. Intellectual property(IP) core assignment and mapping are two key ...Network-on-chip(NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip(SoC) designs. Intellectual property(IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite(E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.60973016 and 61272175)the National Basic Research Program(973) of China(No.2010CB328004)+1 种基金the Youth Backbone Teacher Foundation of Chengdu University of Technology(No.JXGG201305)the Bagui Scholarship Project,China
文摘Network-on-chip(NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip(SoC) designs. Intellectual property(IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite(E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.
