1.Introduction During massive data movements in digital computing systems,several issues have emerged such as high latency,energy ineffi-ciency,and low bandwidth due to the physical separation of pro-cessor and memory...1.Introduction During massive data movements in digital computing systems,several issues have emerged such as high latency,energy ineffi-ciency,and low bandwidth due to the physical separation of pro-cessor and memory units(so-called memory wall)[1-3].To miti-gate the data-movement limitations,three-dimensional(3D)chip integration becomes an optimal solution within von Neumann ar-chitecture since the dense vertical interconnections shorten the distance between chips[4,5].However,the extensively used micro solder bumps for 3D chip stacking impede the further improve-ment of interconnection pitch(<10μm).In this scenario,the Cu/SiO_(2) hybrid bonding technology came into being.Owing to the coexistence of planarized Cu connections and SiO_(2) layers,Cu/SiO_(2) hybrid bonding is the desirable enabler of submicron ultra-dense integration(<1μm),which benefits from Cu-Cu and SiO_(2)-SiO_(2) homogeneous direct bonding replacing micro bumps and underfill[6,7].展开更多
基金financially supported by the National Natural Science Foundation of China(Nos.92164105 and 51975151)the Heilongjiang Provincial Natural Science Foundation of China(No.LH2019E041)the Heilongjiang Touyan Innovation Team Pro-gram(No.HITTY-20190013).
文摘1.Introduction During massive data movements in digital computing systems,several issues have emerged such as high latency,energy ineffi-ciency,and low bandwidth due to the physical separation of pro-cessor and memory units(so-called memory wall)[1-3].To miti-gate the data-movement limitations,three-dimensional(3D)chip integration becomes an optimal solution within von Neumann ar-chitecture since the dense vertical interconnections shorten the distance between chips[4,5].However,the extensively used micro solder bumps for 3D chip stacking impede the further improve-ment of interconnection pitch(<10μm).In this scenario,the Cu/SiO_(2) hybrid bonding technology came into being.Owing to the coexistence of planarized Cu connections and SiO_(2) layers,Cu/SiO_(2) hybrid bonding is the desirable enabler of submicron ultra-dense integration(<1μm),which benefits from Cu-Cu and SiO_(2)-SiO_(2) homogeneous direct bonding replacing micro bumps and underfill[6,7].
