We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre-and post-annealing processes to create a processing strategy for potential applications in nano-dev...We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre-and post-annealing processes to create a processing strategy for potential applications in nano-devices.Starting wafers were co-implanted with indium and C atoms at energies of 70 keV and 10 keV,respectively.A carefully chosen implantation schedule provides an abrupt ultra-shallow junction between 17 and 43 nm with suppressed sheet resistance and appropriate retained sheet carrier concentration at low thermal budget.A defect doping matrix,primarily the behavior and movement of co-implant generated interstitials at different annealing temperatures,may be engineered to form sufficiently activated ultra-shallow devices.展开更多
文摘We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre-and post-annealing processes to create a processing strategy for potential applications in nano-devices.Starting wafers were co-implanted with indium and C atoms at energies of 70 keV and 10 keV,respectively.A carefully chosen implantation schedule provides an abrupt ultra-shallow junction between 17 and 43 nm with suppressed sheet resistance and appropriate retained sheet carrier concentration at low thermal budget.A defect doping matrix,primarily the behavior and movement of co-implant generated interstitials at different annealing temperatures,may be engineered to form sufficiently activated ultra-shallow devices.
