Heterogeneous complementary inverters composed of bi-layer molybdenum disulfide （MoS2） and single-walled carbon-nanotube （SWCNT） networks are designed, and n-type MoS2/p-type SWCNT inverters are fabricated with a ...Heterogeneous complementary inverters composed of bi-layer molybdenum disulfide （MoS2） and single-walled carbon-nanotube （SWCNT） networks are designed, and n-type MoS2/p-type SWCNT inverters are fabricated with a backgated structure. Field-effect transistors （FETs） based on the MoS2 and SWCNT networks show high electrical performance with large ON/OFF ratios up to 106 and 105 for MoS2 and SWCNT, respectively. The MoS2/SWCNT complementary inverters exhibit Vin-Vout signal matching and achieve excellent performances with a high peak voltage gain of 15, a low static-power consumption of a few nanowatts, and a high noise margin of 0.45VDD, which are suitable for future logic-circuit applications. The inverter performances are affected by the channel width-to-length ratios （W/L） of the MOSR-FETs and SWCNT-FETs. Therefore, W/L should be optimized to achieve a tradeoff between the gain and the power consumption.展开更多
基金Acknowledgements This work was supported by the National Natural Science Foundation of China （Nos. 51672154, 51372130, and 61401251）, Open Research Fund Program of the State Key Laboratory of Low-Dimensional Quantum Physics （No. KF201517）, and Open Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices （No. KFJJ201402）.
文摘Heterogeneous complementary inverters composed of bi-layer molybdenum disulfide （MoS2） and single-walled carbon-nanotube （SWCNT） networks are designed, and n-type MoS2/p-type SWCNT inverters are fabricated with a backgated structure. Field-effect transistors （FETs） based on the MoS2 and SWCNT networks show high electrical performance with large ON/OFF ratios up to 106 and 105 for MoS2 and SWCNT, respectively. The MoS2/SWCNT complementary inverters exhibit Vin-Vout signal matching and achieve excellent performances with a high peak voltage gain of 15, a low static-power consumption of a few nanowatts, and a high noise margin of 0.45VDD, which are suitable for future logic-circuit applications. The inverter performances are affected by the channel width-to-length ratios （W/L） of the MOSR-FETs and SWCNT-FETs. Therefore, W/L should be optimized to achieve a tradeoff between the gain and the power consumption.
