Design of Low Power Transmission Gate Based 9T SRAM Cell

Considerable research has considered the design of low-power and high-speed devices.Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices.Embedded static random-access memory(SRAM)units are necessary components in fast mobile computing.Traditional SRAM cells are more energyconsuming and with lower performances.The major constraints in SRAM cells are their reliability and low power.The objectives of the proposed method are to provide a high read stability,low energy consumption,and better writing abilities.A transmission gate-based multi-threshold single-ended Schmitt trigger(ST)9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed.Herein,an ST inverter with a single bit-line design is used to attain the high read stability.A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter.The multithreshold complementary metal oxide semiconductor(MTCMOS)technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM cell.The proposed system uses a combination of standard and ST inverters,which results in a large read stability.Compared with the previous ST 9T,ST 11T,11T,10T,and 7T SRAM cells,the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%,42.09%,31.60%,12.54%,and 31.60%less energy for read operations and 73.59%,93.95%,92.76%,89.23%,and 85.78%less energy for write operations,respectively.

Truncation and Rounding-Based Scalable Approximate Multiplier Design for Computer Imaging Applications

Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a variety of modes based on height(h)and truncation(t)as TRSAM(h,t)in the architecture.This TRSAM operation produces higher absolute error in Least Significant Bit(LSB)data shift unit.A new scalable approximate multiplier approach that uses truncation and rounding TRSAM(3,7)is proposed to increase themultiplier accuracy.With the help of foremost one bit architecture,the proposed scalable approximate multiplier approach reduces the partial products.The proposed approximate TRSAM multiplier architecture gives better results in terms of area,delay,and power.The accuracy of 95.2%and the energy utilization of 24.6 nJ is observed in the proposed multiplier design.The proposed approach shows 0.11%,0.23%,and 0.24%less Mean Absolute Relative Error(MARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.It also shows 0.13%,0.19%,and 0.2%less Variance of Absolute Relative Error(VARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.The proposed approach is implemented with Field-Programmable Gate Array(FPGA)and shows the delay of 3.640,6.481,12.505,22.572,and 36.893 ns for the input of 8-bit,16-bit,32-bit,64-bit,and 128-bit respectively.The proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio(PSNR)of 25.05 dB and Structural Similarity Index Measure(SSIM)of 0.98 with 393 pJ energy consumptions when used in image application.The proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA.

Frequency Domain Adaptive Learning Algorithm for Thoracic Electrical Bioimpedance Enhancement

The Thoracic Electrical Bioimpedance(TEB)helps to determine the stroke volume during cardiac arrest.While measuring cardiac signal it is contaminated with artifacts.The commonly encountered artifacts are Baseline wander(BW)and Muscle artifact(MA),these are physiological and nonstationary.As the nature of these artifacts is random,adaptive filtering is needed than conventional fixed coefficient filtering techniques.To address this,a new block based adaptive learning scheme is proposed to remove artifacts from TEB signals in clinical scenario.The proposed block least mean square(BLMS)algorithm is mathematically normalized with reference to data and error.This normalization leads,block normalized LMS(BNLMS)and block error normalized LMS(BENLMS)algorithms.Various adaptive artifact cancellers are developed in both time and frequency domains and applied on real TEB quantities contaminated with physiological signals.The ability of these techniques is measured by calculating signal to noise ratio improvement(SNRI),Excess Mean Square Error(EMSE),and Misadjustment(Mad).Among the considered algorithms,the frequency domain version of BENLMS algorithm removes the physiological artifacts effectively then the other counter parts.Hence,this adaptive artifact canceller is suitable for real time applications like wearable,remove health care monitoring units.

QCA with reversible arithmetic and logic unit for nanoelectronics applications

Purpose-In this research work,brief quantum-dot cellular automata(QCA)concepts are discussed through arithmetic and logic units.This work is most useful for nanoelectronic applications,VLSI industry mainly depends on this type of fault-tolerant QCA based arithmetic logic unit(ALU)design.The ALU design is mainly depending on set instructions and rules;these are maintained through low-power ultra-functional tricks only possible with QCA-based reversible arithmetic and logic unit for nanoelectronics.The main objective of this investigation is to design an ultra-low power and ultra-high-speed ALU design with QCA technology.The following QCA method has been implemented through reversible logic.Design/methodology/approach-QCA logic is the main and critical condition for realizing NANO-scale design that delivers considerably fast integrate module,effective performable computation and is less energy efficiency at the nano-scale(QCA).Processors need an ALU in order to process and calculate data.Faultresistant ALU in QCA technology utilizing reverse logic is the primary objective of this study.There are now two sections,i.e.reversible ALU(RAU),logical(LAU)and arithmetical(RAU).Findings-A reversible 231 multiplexer based on the Fredkin gate(FRG)was developed to allow users to choose between arithmetic and logical operations.QCA full adders are also implemented to improve arithmetic operations’performance.The ALU is built using reversible logic gates that are fault-tolerant.Originality/value-In contrast to earlier research,the suggested reversible multilayeredALU with reversible QCA operation is imported.The 8-and 16-bit ALU,as well as logical unit functioning,is designed through fewer gates,constant inputs and outputs.This implementation is designed on the Mentor Graphics QCA tool and verifies all functionalities.