The fundamental operating principle of a Class F power amplifier and the factors aiding or affecting Class F performance were explicated previously. A Class F power amplifier design which satisfies WCDMA specification...The fundamental operating principle of a Class F power amplifier and the factors aiding or affecting Class F performance were explicated previously. A Class F power amplifier design which satisfies WCDMA specifications is explained in this paper. The Class F amplifier was designed by employing Motorola’s LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor models and we simulated its performance by means of ADS. A variety of procedures were applied in the process of designing Class F amplifier, namely, DC simulation, bias point selection, source-pull and load-pull characterization, input and output matching circuit design and the design of suitable harmonic traps, which are explained here.展开更多
This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4...This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.展开更多
文摘The fundamental operating principle of a Class F power amplifier and the factors aiding or affecting Class F performance were explicated previously. A Class F power amplifier design which satisfies WCDMA specifications is explained in this paper. The Class F amplifier was designed by employing Motorola’s LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor models and we simulated its performance by means of ADS. A variety of procedures were applied in the process of designing Class F amplifier, namely, DC simulation, bias point selection, source-pull and load-pull characterization, input and output matching circuit design and the design of suitable harmonic traps, which are explained here.
文摘This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.
