Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28...Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.展开更多
As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of th...As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61434007 and 61376109)
文摘Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.
基金supported by the National Natural Science Foundation of China(No.61434007)the National Natural Science Foundation of China(No.61704192)
文摘As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.
