Effect of defects properties on InP-based high electron mobility transistors

The performance damage mechanism of InP-based high electron mobility transistors(HEMTs) after proton irradiation has been investigated comprehensively through induced defects.The effects of the defect type, defect energy level with respect to conduction band ET, and defect concentration on the transfer and output characteristics of the device are discussed based on hydrodynamic model and Shockley–Read–Hall recombination model.The results indicate that only acceptorlike defects have a significant influence on device operation.Meanwhile, as defect energy level ETshifts away from conduction band, the drain current decreases gradually and finally reaches a saturation value with ETabove 0.5 eV.This can be attributed to the fact that at sufficient deep level, acceptor-type defects could not be ionized any more.Additionally,the drain current and transconductance degrade more severely with larger acceptor concentration.These changes of the electrical characteristics with proton radiation could be accounted for by the electron density reduction in the channel region from induced acceptor-like defects.

Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAIAs/InGaAs InP-based HEMTs

A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.