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Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation 被引量:1
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作者 Kai HUANG Xiao-lang YAN +6 位作者 Sang-il HAN soo-ik chae Ahmed A. JERRAYA Katalin POPOVICI Xavier GUERIN Lisane BRISOLARA Luigi CARRO 《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》 SCIE EI CAS CSCD 2009年第2期151-164,共14页
The application-specific multiprocessor system-on-chip(MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications,which require both high performance and flexible pr... The application-specific multiprocessor system-on-chip(MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications,which require both high performance and flexible programmability. As an effective method for MPSoC development,we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels:Simulink combined algorithm and architecture model(CAAM),virtual architecture(VA),transactional accurate architecture(TA),virtual prototype(VP) and field-programmable gate array(FPGA) emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model,allowing processor,communication and tasks design space exploration. 展开更多
关键词 Multiprocessor system-on-chip (MPSoC) design REFINEMENT Simulink SYSTEMC Motion-JPEG H.264
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