如何正确和安全地开展后量子密码算法的相关实现

后量子密码(PQC)算法的提出源于非对称密码的新需求.其主要包括密钥交换、非对称加密和数字签名.后量子密码算法的加密计算环节,需要同时抵御传统计算机以及量子计算机的破解和攻击.然而,PQC算法本身仍然需要进行一些基于常规数学函数的软件或者硬件实现.因此,通常的基于实现层面的攻击仍然有效.PQC算法的一些功能,例如有限域的取模、求逆、非均匀随机数采样以及解码算法等,已经采用了“常数时间”等相关防御实现,对其开展评估具有很大的难度.本文主要列举了PQC在实现过程中可能面临的挑战,特别是与旁路分析相关的泄漏,并进行更加深入的检测和研究.首先,我们详细说明了对条件控制语句以及条件访问数据结构中存在的旁路泄漏的探测与预防方法.其次,在操作数据被分成若干块(即掩码防御方法)的条件下,传统的纵向泄漏检测方法并不适用,但是我们的前述方法却可以适用于数据旁路的泄漏检测.本文反映出PQC算法的安全实现仍然需要安全评估以及安全编码等相关的知识.本文主要介绍了一种通用的检测方法,应对多种PQC算法存在不同算法类型、不同数学类型及其不同参数配置的复杂问题,并旨在给读者提供关于安全代码实现评估和设计的全面介绍.

Information Theoretic Distinguishers for Timing Attacks with Partial Profiles: Solving the Empty Bin Issue

In any side-channel attack, it is desirable to exploit all the available leakage data to compute the distinguisher’s values. The profiling phase is essential to obtain an accurate leakage model, yet it may not be exhaustive. As a result, information theoretic distinguishers may come up on previously unseen data, a phenomenon yielding empty bins. A strict application of the maximum likelihood method yields a distinguisher that is not even sound. Ignoring empty bins reestablishes soundness, but seriously limits its performance in terms of success rate. The purpose of this paper is to remedy this situation. In this research, we propose six different techniques to improve the performance of information theoretic distinguishers. We study them thoroughly by applying them to timing attacks, both with synthetic and real leakages. Namely, we compare them in terms of success rate, and show that their performance depends on the amount of profiling, and can be explained by a bias-variance analysis. The result of our work is that there exist use-cases, especially when measurements are noisy, where our novel information theoretic distinguishers (typically the soft-drop distinguisher) perform the best compared to known side-channel distinguishers, despite the empty bin situation.

在芯片硅前阶段对侧信道攻击防护能力验证的重要性

侧信道攻击技术越来越受到业界的重视,同时越来越多的标准和认证体系均增加了防护侧信道攻击能力评判的需求,如中国数字版权管理体系中的Enhanced Profile。本文阐述了在芯片的硅前(Pre-silicon)设计阶段对处理重要信息和内容的系统模块抗攻击性能(特别是针对侧信道攻击)进行验证的重要性,并介绍了一种名为"Virtualyzr"的工具,该工具可以验证在RTL(Register Transfer Level)设计阶段芯片对侧信道攻击的防护能力,该工具将侧信道攻击漏洞转化为设计代码中的漏洞,进而帮助设计人员实现更为安全的设计。