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Automatic Circuit Extractor for HDL Description Using Program Slicing 被引量:1
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作者 tunli yangguo si-kunli 《Journal of Computer Science & Technology》 SCIE EI CSCD 2004年第5期718-728,共11页
Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation,... Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG), etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain, it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach. 展开更多
关键词 program slicing chaining slice process dependence graph circuit extraction VLSI functional verification
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面向HDL描述基于程序切片的自动电路抽取技术研究与实现
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作者 tunli yangguo si-kunli 《Journal of Computer Science & Technology》 SCIE EI CSCD 2004年第C00期96-96,共1页
现代集成电路设计复杂性在不断增加,而对整个设计进行验证的效率却太低。因此,在形式化验证和模拟验证时,必须采用不同的技术来对设计中的数据通路部分和控制部分分别加以验证。大多数的验证策略都是通过从HDL设计描述中为感兴趣的... 现代集成电路设计复杂性在不断增加,而对整个设计进行验证的效率却太低。因此,在形式化验证和模拟验证时,必须采用不同的技术来对设计中的数据通路部分和控制部分分别加以验证。大多数的验证策略都是通过从HDL设计描述中为感兴趣的部分设计提取出有用的验证信息来实现的。 展开更多
关键词 程序切片 数据通路 形式化验证 HDL 描述 抽取 集成电路设计 模拟验证
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