A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and it...A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.展开更多
As the wireless sensor networks are easily deployable, the volume of sensor applications has been increased widely in various fields of military and commercial areas. In order to attain security on the data exchanged ...As the wireless sensor networks are easily deployable, the volume of sensor applications has been increased widely in various fields of military and commercial areas. In order to attain security on the data exchanged over the network, a hybrid cryptographic mechanism which includes both symmetric and asymmetric cryptographic functions is used. The public key cryptographic ECC security implementation in this paper performs a matrix mapping of data’s at the points on the elliptical curve, which are further encoded using the private symmetric cipher cryptographic algorithm. This security enhancement with the hybrid mechanism of ECC and symmetric cipher cryptographic scheme achieves efficiency in energy conservation of about 7% and 4% compared to the asymmetric and symmetric cipher security implementations in WSN.展开更多
文摘A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.
文摘As the wireless sensor networks are easily deployable, the volume of sensor applications has been increased widely in various fields of military and commercial areas. In order to attain security on the data exchanged over the network, a hybrid cryptographic mechanism which includes both symmetric and asymmetric cryptographic functions is used. The public key cryptographic ECC security implementation in this paper performs a matrix mapping of data’s at the points on the elliptical curve, which are further encoded using the private symmetric cipher cryptographic algorithm. This security enhancement with the hybrid mechanism of ECC and symmetric cipher cryptographic scheme achieves efficiency in energy conservation of about 7% and 4% compared to the asymmetric and symmetric cipher security implementations in WSN.
