In this paper we present a concept of new architectural model consisting of multiple loop delay to increase the throughput. The simulated behavior of an optical node has been realized by using an n x m optical switch ...In this paper we present a concept of new architectural model consisting of multiple loop delay to increase the throughput. The simulated behavior of an optical node has been realized by using an n x m optical switch and recirculating optical delay lines. This investigation infers the scaling behaviors of the proposed architec-ture to maintain efficient use of the buffer under Poisson traffic loading. The analysis also reports the traffic handling capacity for the given complexity of the node architectural design.展开更多
In this paper we propose a new architectural switching nodes consisting of two processing nodes that follow Erlang B and Erlang C traffic respectively. The developed model is used to best utilize the given number of o...In this paper we propose a new architectural switching nodes consisting of two processing nodes that follow Erlang B and Erlang C traffic respectively. The developed model is used to best utilize the given number of output channels to achieve the least blocking probability. An appropriate mathematical model has been further devised and its call blocking probability has been enunciated. Performance of the model has been evaluated for different values of blocking probabilities. It has been observed that the performance of the network is well satisfactory for different design parameters.展开更多
文摘In this paper we present a concept of new architectural model consisting of multiple loop delay to increase the throughput. The simulated behavior of an optical node has been realized by using an n x m optical switch and recirculating optical delay lines. This investigation infers the scaling behaviors of the proposed architec-ture to maintain efficient use of the buffer under Poisson traffic loading. The analysis also reports the traffic handling capacity for the given complexity of the node architectural design.
文摘In this paper we propose a new architectural switching nodes consisting of two processing nodes that follow Erlang B and Erlang C traffic respectively. The developed model is used to best utilize the given number of output channels to achieve the least blocking probability. An appropriate mathematical model has been further devised and its call blocking probability has been enunciated. Performance of the model has been evaluated for different values of blocking probabilities. It has been observed that the performance of the network is well satisfactory for different design parameters.
