The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of t...The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be ob-tained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ter-nary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are charac-terized with distinctive low power consumption.展开更多
基金Supported by the National Natural Science Foundation of China(No.60776022,No.60971061,No.61076032)the Key Project of Natural Scence Foundation of Zhejiang Province,China(No.21111219)+1 种基金the New Shoot Talents Program of Zhejing Province(No.2008R40G2070015)the Student Scientific Research Innovation Project of Zhejiang Province
文摘The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be ob-tained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ter-nary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are charac-terized with distinctive low power consumption.
