The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low...The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low power characteristics.An improved biased architecture is adopted in the second stage to attain a better gain-compensation performance.The design is verified with TSMC standard 1 P6 M 0.18μm RF CMOS process.The measurement results show that the parasitic problem of the transistors at high frequencies is solved.A high and flat S21 of 9.7±1.5 dB and the lowest NF 3.5 dB are achieved in the desired frequency band.The power consumption is only 7.5 mA under 1.6 V supply.The proposed LNA achieves broadband flat gain,low noise,and high linearity performance simultaneously,allowing it to be used in 3-10 GHz UWB applications.展开更多
A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is cho...A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.展开更多
A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V...A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 dBm.At output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,respectively.The chip size is 1.27mm ×0.9mm.展开更多
A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is...A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.展开更多
A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ...A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.展开更多
基金Supported by the National Natural Science Foundation of China(No.61534003,61874024,61871116)
文摘The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low power characteristics.An improved biased architecture is adopted in the second stage to attain a better gain-compensation performance.The design is verified with TSMC standard 1 P6 M 0.18μm RF CMOS process.The measurement results show that the parasitic problem of the transistors at high frequencies is solved.A high and flat S21 of 9.7±1.5 dB and the lowest NF 3.5 dB are achieved in the desired frequency band.The power consumption is only 7.5 mA under 1.6 V supply.The proposed LNA achieves broadband flat gain,low noise,and high linearity performance simultaneously,allowing it to be used in 3-10 GHz UWB applications.
基金Supported by the National Natural Science Foundation of China （No. 60576028） and the National High Technology Research and Development Program of China （No. 2007AA01Z2a5）
基金Supported by the National Natural Science Foundation of China(No.61534003)
文摘A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.
基金Supported by the Natural Science Foundation of Jiangsu Province （ BK2010411 ） and the National International Cooperation Project of China-Korea （2011DFA11310）.
基金Supported by the High Technology Research and Development Programme of China (2006AA03Z418)
文摘A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 dBm.At output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,respectively.The chip size is 1.27mm ×0.9mm.
文摘A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.
基金supported by Open Project of State Key Laboratory of Millimeter Waves (K201727)Open Project of National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology (KFJJ20170203)+1 种基金National Science Foundation (61571235, 61504065)Scientific Research Foundation of Nanjing University of Posts and Telecommunications (NUPTSF NY215138)
文摘A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.
