This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratio...This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.展开更多
Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (...Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (BTBT) leakages are considered three maindeterminants of total leakage current. Up to now, how to accurately estimate leakage current oflarge-scale circuits within endurable time remains unsolved, even though accurate leakage modelshave been widely discussed. In this paper, the authors first dip into the stack effect of CMOStechnology and propose a new simple gate-level leakage current model. Then, a table-lookup basedtotal leakage current simulator is built up according to the model. To validate the simulator,accurate leakage current is simulated at circuit level using popular simulator HSPICE forcomparison. Some further studies such as maximum leakage current estimation, minimum leakage currentgeneration and a high-level average leakage current macromodel are introduced in detail.Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage currentestimation methods are very accurate and efficient.展开更多
Design, test and verification of today's VLSI circuits continuously challenge engineers in every IC design cycle. Based on the Twelfth IEEE Asian Test Symposium (Xi'an, November 16-19, 2003) and the Fourth IEE...Design, test and verification of today's VLSI circuits continuously challenge engineers in every IC design cycle. Based on the Twelfth IEEE Asian Test Symposium (Xi'an, November 16-19, 2003) and the Fourth IEEE Workshop on RTL and High-Level Testing (Xi'an, November 20-21, 2003), we are encouraged to organized a special issue on these topices.展开更多
基金国家自然科学基金，the Sci. & Technol. Project of Beijing，中国科学院资助项目，Synopsys公司资助项目
文摘This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.
文摘Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (BTBT) leakages are considered three maindeterminants of total leakage current. Up to now, how to accurately estimate leakage current oflarge-scale circuits within endurable time remains unsolved, even though accurate leakage modelshave been widely discussed. In this paper, the authors first dip into the stack effect of CMOStechnology and propose a new simple gate-level leakage current model. Then, a table-lookup basedtotal leakage current simulator is built up according to the model. To validate the simulator,accurate leakage current is simulated at circuit level using popular simulator HSPICE forcomparison. Some further studies such as maximum leakage current estimation, minimum leakage currentgeneration and a high-level average leakage current macromodel are introduced in detail.Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage currentestimation methods are very accurate and efficient.
文摘Design, test and verification of today's VLSI circuits continuously challenge engineers in every IC design cycle. Based on the Twelfth IEEE Asian Test Symposium (Xi'an, November 16-19, 2003) and the Fourth IEEE Workshop on RTL and High-Level Testing (Xi'an, November 20-21, 2003), we are encouraged to organized a special issue on these topices.
