A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Reliability study of custom designed ADC for the Jiangmen underground neutrino observatory

Objective The Jiangmen underground neutrino observatory(JUNO)is the largest and most precise liquid scintillator detector under construction in the south of China.The front-end readout electronics system will be installed very close to the photomultiplier tubes under water.Therefore,the system’s absolute reliability is mandatory.As an important piece,the failure rate of the custom designed analog-to-digital convertor(ADC)must be measured.Methods The Arrhenius High Temperature Operating Life(HTOL)model is usually used to calculate the standard reliability value failure rate(λ).A temperature acceleration test of the ADC is performed with a 115℃ambient temperature based on a custom aging system.The performance of ADC is compared before and after aging,and the most significant bit(MSB)of the digital output is monitored during the test.Results The result of a 2400-hour-long test shows that there were no failures.The upper limit of the failure rate is calculated as 5.8FIT,which can be added to the failure rate of other components to meet the overall failure rate requirements(84FIT).Conclusion With the test system,we established a method based on the HTOL model to obtain the upper limit of the ADC reliability for overall failure rate calculation in JUNO.This method can be applied to the reliability measurement for any other custom designed ADC.This experiment can be repeated with a new set of parameters to get a satisfactory failure rate according to other overall system requirements.

FPGA implementation of 10 G Ethernet-based DAQ systems for pixel detectors

Background High Energy Photon Source-Test Facility is a project to study and verify the feasibility of the key technologies which will be applied to that of High Energy Photon Source(HEPS).The pixel array detector is one of the most important components of synchrotron radiation detection.Purpose In order to meet the requirements of the X-ray detection of HEPS,it was asked to independently develop a pixel array detector prototype with an effective detection area larger than 8×8 cm^(2),a spatial resolution better than 200 pm,a detectable energy range from 8 to 20 keV,and a frame rate higher than 1 kHz.The readout electronics system using the field-programmable gate array(FPGA)as its core of the digital logic makes the basic functions of the detector prototype feasibility by implementing all the configuration and data readout of the BPIX which is the dedicated pixel readout chip designed for Chinese next generation of synchrotron light source and working in the single-photon counting mode.Considering the large amount of data generated by pixel detectors and the demand for real-time data acquisition at higher frame rates,a firmware based on the TCP/IP protocol was developed in FPGA.Methods The implementation of 1 G/10 G Ethernet hub firmware provides a method of processing multi-ports Gigabit data and improving bandwidth.The key idea is the conversion of the GMII/XGMII bus in 1 G/10 G Ethernet protocol and the Arbitrator module applying Round-Robin algorithms.Results and conclusion The firmware converts and gathers TCP/IP frames from Gigabit network to 10-Gigabit network successfully.Through measurement,the bandwidth of the hub can reach 8.57 Gbps.A pixel detector integrated with 1 G/10 G Ethernet hub completes the readout of large flux data on 1.5 mega pixels detector at 1.2 kHz frame rate.

A high time resolution and low-power ASIC for MRPC applications

Purpose The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber(MRPC)in Beijing SpectrometerⅢexperiments,posing a demand for the high time resolution and low-power electronics.Methods Considering MRPC features,an application-specific integrated circuit(ASIC)called FEEWAVE,which integrates the front-end circuit and digitization function,is proposed to meet the above requirements.The front-end circuit implements I/V conversion and signal amplification.To reduce power consumption and further improve the time resolution,the waveform sampling technique based on switch capacitor array is adopted.Results and conclusion A 30 fC to 1.2 pC input signal dynamic range is obtained,and the jitter is less than 21 ps rms.At the same time,the chip realizes 5 GSPS(gigabit samples per second)sampling rate,trigger rate capability of 50 kHz and 25 mW/channel power consumption.The 6-channel ASIC has been designed and taped out with 0.18μm complementary metal oxide semiconductor technology.The preliminary test results of FEEWAVE have been achieved.

Study on low noise cryogenic charge readout electronics for liquid xenon time projection chamber

Background Liquid xenon time projection chamber(LXe TPC)is widely used in high-energy physics experiments such as particle detection and neutrino(or neutrinoless)double beta decay.The charge readout accuracy of the LXeTPCdirectly affects the measurement results and success of the experiments.Because liquid xenon needs to maintain a cryogenic temperature between 162 and 165 K at atmospheric pressure,the charge generated in the LXe TPC always needs to be read out in the cryogenic environment for minimizing the input capacitance,which has effect in determining the output noise of the charge amplifier.Purpose Design a charge readout electronics system applicable to LXe TPC and research a data analysis method to get the exact amount of charge by analyzing the waveform at that output of the designed electronics system.Methods Design a multi-channel charge-reading application specific integrated circuit(ASIC)that can operate in the cryogenic environment.The signals and power supply of the ASIC are connected to an electronics system at room temperature through micro-coaxial cables.The electronics at room temperature complete the sampling of the ASIC output.A data acquisition device receives the sampled waveform data and calculates the charge measurement resolution by Gaussian fitting.Results The designed ASIC and selected micro-coaxial cable can work in stable condition under the cryogenic environment of 165 K.The analyzed integral nonlinearity of the charge measurement of the chip is 0.83%in the range from 1 to 50 fC,and the charge measurement resolution of the chip is lower than 900 e−RMS.Conclusion In this paper,a preliminary study of the charge readout method based on the system structure of self-developed ASIC,micro-coaxial cable,and data readout electronics is completed for LXe TPC.The system test results indicate that the designed ASIC can work normally in the cryogenic temperature of 165 K with a high dynamic range and good linearity of the charge measurement.Further work can be done to reduce the charge measurement resolution of the system to 200 e−RMS.

The development and application of the test system for the silicon pixel modules in HEPS-BPIX

Background HEPS-BPIX is a prototype of photon counting pixel detector developed for the High Energy Photon Source.It consists of 16 silicon pixel modules which should be tested individually to ensure the function and performance.Purpose Due to various factors such as the non-uniformity of the processes and voltage drop,the response of each pixel in the silicon pixel module is not identical completely.The response difference of pixels can be minimized by the threshold calibration.This system is developed for the quality test and calibration of the silicon pixel modules.Methods The system consists of a mother board,a control board and a data acquisition(DAQ)system.The mother board provides necessary resources including power supplies and the fanout of calibration signals.Besides,it can be used to test the connectivity by monitoring the power states.The control board reads data out and provides the clock,trigger and configuration data for the silicon pixel module.The DAQ system sends the control commands and receives the readout data through an Ethernet link.Results Compared with the previous readout system,this designed system has a lower noise level and better scanning curves making the calibration more accurate.And it has been successfully applied to the comparison experiments of the through silicon via and wire-bonding silicon pixel modules.Conclusion The results show that this test system can be used to the quality test and calibration of the silicon pixel modules.In addition,the system can be adapted to the measurement of different pixel array detector modules.

Design of a MAPS readout electronics prototype for BESIII inner tracker

Background The spatial resolution and the reconstruction efficiency of the main drift chamber of the Beijing Spectrometer III has degraded aftermore than nine years of operation.An improved new inner drift chamber has been constructed to replace the old chamber in case of the radiation damage.Amonolithic active pixel sensor(MAPS)based detector prototype is selected as one of the prototype schemes for the inner chamber upgrade.Purpose Design a set of MAPS readout electronics system for the inner drift chamber upgrade.This system can verify the function and performance of the selected MAPS chip and discover the matters needing attention when designing large-scale detectors.Methods The electronics system design is composed of three parts.The first part is flexible printed circuit boards(PCBs)assembled with the MAPS chips.The second part is digital readout boards,which are connected to the flexible PCBs via FPGA mezzanine card cables.The digital readout board realizes the configuration of the MAPS chip register,receives and processes the data output by the MAPS chip,and transfers the processed data to the DAQ device.The third part includes a readout control board and two fan-out boards that used to separately fan out the trigger signal and the start signal to all the digital readout boards.Results and conclusion AMAPS readout electronics system consisting of five MAPS based detector prototypes is designed.The system can work stably under the electron beam experimental conditions with a frequency up to 2 kHz and energy ranging from 1 to 5 GeV.The system detection efficiency of the electron beam is∼95%,and the spatial resolution is∼5.3μm at electron energies of 1 GeV.The design of the electronics system meets the requirements for verifying the performance of the MAPS chips and the technical feasibility of the detector structure.

Development and study of an imaging detector based on high-position resolution THGEM

Introduction THickGaseous Electron Multiplier(THGEM)has many advantages while the moderate position resolution is regarded as the main inferiority comparing with the traditional GEM,so this limits the applications of THGEM,such as X-ray imaging and charge particle tracking.Materials and methods By improving the production techniques,THGEMs with smaller pitch and hole diameter can be made,i.e.,0.4 and 0.15 mm by mechanical drilling,and 0.3 and 0.1 mm by laser etching,respectively.Based on the new THGEMs,a two-dimensional imaging detector with 50×50mm sensitive area was developed for 0.1∼50 MeVlow-energy electrons detection and reaching better than 100μm position resolution(sigma).At the same time,a set of front-end electronics was developed based on homemade ASIC chips,i.e.,Charge Amplifier and Shaping Amplifier for GEM(CASAGEM),and applied successfully to the detector.Conclusion The X-ray and beam tests results indicate that both detector and Front End Electronics(FEE)worked well,and the position resolution achieved 74.9μm by using the charge center-of-gravity method.This indicates that the high-position resolution THGEM is promising for imaging and tracking application.