As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they ...As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.展开更多
Often referred to as the“Third Pole,”China’s Qinghai-Tibetan Plateau developed large amounts of peatland owing to its unique alpine environment.As a renewable resource,peat helps to regulate the climate as well as ...Often referred to as the“Third Pole,”China’s Qinghai-Tibetan Plateau developed large amounts of peatland owing to its unique alpine environment.As a renewable resource,peat helps to regulate the climate as well as performing other important functions.However,in recent years,intensifying climate change and anthropogenic disturbances have resulted in peatland degradation and consequently made sustainable development of peatland more difficult.This review summarizes peatland ecological and economic functions,including carbon sequestration,biodiversity conservation,energy supplies,and ecotourism.It identifies climate change and anthropogenic disturbances as the two key factors attributing to peatland degradation and ecosystem carbon loss.Current problems in environmental degradation and future challenges in peatland management under the effects of global warming are also discussed and highlighted.展开更多
Electrocardiogram（ECG） can be used as a valid way for diagnosing heart disease.To fulfill ECG processing in wearable devices by reducing computation complexity and hardware cost,two kinds of adaptive filters are des...Electrocardiogram（ECG） can be used as a valid way for diagnosing heart disease.To fulfill ECG processing in wearable devices by reducing computation complexity and hardware cost,two kinds of adaptive filters are designed to perform QRS complex detection and motion artifacts removal,respectively.The proposed design achieves a sensitivity of 99.49% and a positive predictivity of 99.72%,tested under the MIT-BIH ECG database.The proposed design is synthesized under the SMIC 65-nm CMOS technology and verified by post-synthesis simulation.Experimental results show that the power consumption and area cost of this design are of 160 μW and 1.09×10^5 μm^2,respectively.展开更多
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.
基金This study was financially supported by the National Natural Science Foundation of China(41671244)China Postdoctoral Science Foundation Grant(2016M600751)+2 种基金a fund from Chengdu Institute of Biology,Chinese Academy of Sciences(KXYS20S1501)It is also supported by the National Basic Research Program of China(2014CB846003)China’s QianRen Program and a merit scholarship program for foreign students from Quebec,Canada,to G.Yang.We also thank Dr.Yongheng Gao for providing us the photo of grassland in QTP,and Dr.Mei Wang for her constructive suggestion for im-proving this paper.
文摘Often referred to as the“Third Pole,”China’s Qinghai-Tibetan Plateau developed large amounts of peatland owing to its unique alpine environment.As a renewable resource,peat helps to regulate the climate as well as performing other important functions.However,in recent years,intensifying climate change and anthropogenic disturbances have resulted in peatland degradation and consequently made sustainable development of peatland more difficult.This review summarizes peatland ecological and economic functions,including carbon sequestration,biodiversity conservation,energy supplies,and ecotourism.It identifies climate change and anthropogenic disturbances as the two key factors attributing to peatland degradation and ecosystem carbon loss.Current problems in environmental degradation and future challenges in peatland management under the effects of global warming are also discussed and highlighted.
基金supported by the National Natural Science Foundation of China(Nos.61574040,61234002,61525401)
文摘Electrocardiogram（ECG） can be used as a valid way for diagnosing heart disease.To fulfill ECG processing in wearable devices by reducing computation complexity and hardware cost,two kinds of adaptive filters are designed to perform QRS complex detection and motion artifacts removal,respectively.The proposed design achieves a sensitivity of 99.49% and a positive predictivity of 99.72%,tested under the MIT-BIH ECG database.The proposed design is synthesized under the SMIC 65-nm CMOS technology and verified by post-synthesis simulation.Experimental results show that the power consumption and area cost of this design are of 160 μW and 1.09×10^5 μm^2,respectively.
