This paper presents an 11-bit 200MS/s subrange S AR ADC with an integrated reference buffer in 65nm CMOS.The proposed ADC employs a 3.5-bit flash ADC for coarse conversion,and a compact timing scheme at the flash/SAR ...This paper presents an 11-bit 200MS/s subrange S AR ADC with an integrated reference buffer in 65nm CMOS.The proposed ADC employs a 3.5-bit flash ADC for coarse conversion,and a compact timing scheme at the flash/SAR boundary to speed up the conversion.The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation.Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation.In addition,the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3dB at 200MS/s.It consumes 3.91mW from a 1.2V supply,including the reference buffer.展开更多
基金supported by the Zhongxing Telecommunication Equipment CorporationBeijing Microelectronics Technology Institute
文摘This paper presents an 11-bit 200MS/s subrange S AR ADC with an integrated reference buffer in 65nm CMOS.The proposed ADC employs a 3.5-bit flash ADC for coarse conversion,and a compact timing scheme at the flash/SAR boundary to speed up the conversion.The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation.Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation.In addition,the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3dB at 200MS/s.It consumes 3.91mW from a 1.2V supply,including the reference buffer.
