The successive approximation register(SAR)is one of the most energy-efficient analog-to-digital converter(ADC)architecture for medium-resolution applications.However,its high energy efficiency quickly diminishes when ...The successive approximation register(SAR)is one of the most energy-efficient analog-to-digital converter(ADC)architecture for medium-resolution applications.However,its high energy efficiency quickly diminishes when the target resolution increases.This is because a SAR ADC suffers from several major error source,including the sampling kT/C noise,the comparator noise,and the DAC mismatch.These errors are increasing hard to address in high-resolution SAR ADCs.This paper reviews recent advances on error suppression techniques for SAR ADCs,including the sampling kT/C noise reduction,the noise-shaping(NS)SAR,and the mismatch error shaping(MES).These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.展开更多
Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout a...Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.展开更多
基金supported by National Natural Science Foundation of China(No.61904094,No.61934009)China Postdoctoral Science Foundation(No.2020M670329)Beijing Innovation Center for Future Chips(ICFC).
文摘The successive approximation register(SAR)is one of the most energy-efficient analog-to-digital converter(ADC)architecture for medium-resolution applications.However,its high energy efficiency quickly diminishes when the target resolution increases.This is because a SAR ADC suffers from several major error source,including the sampling kT/C noise,the comparator noise,and the DAC mismatch.These errors are increasing hard to address in high-resolution SAR ADCs.This paper reviews recent advances on error suppression techniques for SAR ADCs,including the sampling kT/C noise reduction,the noise-shaping(NS)SAR,and the mismatch error shaping(MES).These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.
基金supported in part by the NSF under Grant No.1704758,and the DARPA IDEA program.
文摘Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.
