A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST).The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control.In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation.The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing.The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI).In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption.Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm 2 .The measurement results show that this transceiver can achieve bit error rate (BER)< 10 -12 after a 15.3 dB loss channel at 20 GHz.

Co‑packaged optics(CPO):status,challenges,and solutions

Due to the rise of 5G,IoT,AI,and high-performance computing applications,datacenter trafc has grown at a compound annual growth rate of nearly 30%.Furthermore,nearly three-fourths of the datacenter trafc resides within datacenters.The conventional pluggable optics increases at a much slower rate than that of datacenter trafc.The gap between application requirements and the capability of conventional pluggable optics keeps increasing,a trend that is unsustainable.Copackaged optics(CPO)is a disruptive approach to increasing the interconnecting bandwidth density and energy efciency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics.CPO is widely regarded as a promising solution for future datacenter interconnections,and silicon platform is the most promising platform for large-scale integration.Leading international companies(e.g.,Intel,Broadcom and IBM)have heavily investigated in CPO technology,an inter-disciplinary research feld that involves photonic devices,integrated circuits design,packaging,photonic device modeling,electronic-photonic co-simulation,applications,and standardization.This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform,identify the key challenges,and point out the potential solutions,hoping to encourage collaboration between diferent research felds to accelerate the development of CPO technology.