Charge transport and quantum confinement in MoS2 dual-gated transistors

Semiconductive two dimensional(2D)materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices.In this work,we investigate the MoS2 field-effect transistors(FETs)with a dual-gated(DG)architecture,which consists of symmetrical thickness for back gate(BG)and top gate(TG)dielectric.The thickness-dependent charge transport in our DG-MoS2 device is revealed by a four-terminal electrical measurement which excludes the contact influence,and the TCAD simulation is also applied to explain the experimental data.Our results indicate that the impact of quantum confinement effect plays an important role in the charge transport in the MoS2 channel,as it confines charge carriers in the center of the channel,which reduces the scattering and boosts the mobility compared to the single gating case.Furthermore,temperature-dependent transfer curves reveal that multi-layer MoS2 DG-FET is in the phonon-limited transport regime,while single layer MoS2 shows typical Coulomb impurity limited regime.

Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

The investigation of two-dimensional(2D)materials has advanced into practical device applications,such as cascaded logic stages.However,incompatible electrical properties and inappropriate logic levels remain enormous challenges.In this work,a doping-free strategy is investigated by top gated(TG)MoS_(2) field-effect transistors(FETs)using various metal gates(Au,Cu,Ag,and Al).These metals with different work functions provide a convenient tuning knob for controlling threshold voltage(V_(th))for MoS_(2) FETs.For instance,the Al electrode can create an extra electron doping(n-doping)behavior in the MoS_(2) TG-FETs due to a dipole effect at the gate-dielectric interface.In this work,by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit,we successfully demonstrate wafer-scale MoS_(2) inverter arrays with an optimized inverter switching threshold voltage(V_(M))of 1.5 V and a DC voltage gain of 27 at a supply voltage(V_(DD))of 3 V.This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS_(2) film.

A novel contact engineering method for transistors based on two-dimensional materials

Contact engineering is of critical importance for two-dimensional(2D)transition metal dichalcogenide(TMD)-based devices.However,there are only a few solutions to overcome this obstacle because of the complexity of the TMD-contact interface.In this work,we propose a novel method using a soft plasma treatment followed by the seamless deposition of a metal electrode to reduce the contact resistance of MoS_(2)field effect transistors(FETs).The treated FETs exhibit three times higher mobility than the control FETs without plasma treatment.The soft plasma treatment can remove the facial sulfur atoms and expose the middle Mo atoms so that they come into direct contact with the metal electrode,thus greatly improving the contact behavior.First-principles calculation is also performed to support the experimental results.Our potentially scalable strategy can be extended to the whole family of TMD based FETs to provide a possible route of device processsing technology for 2D device application.