Spear and Shield： Evolution of Integrated Circuit Camouflaging

Intellectual property （IP） protection is one of the hardcore problems in hardware security. Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse engineering （RE） based attacks. Integrated circuit （IC） camouflaging technique fills this gap by replacing some conventional logic gates in tile IPs with specially designed logic cells （called camouflaged gates） without changing the functions of tile IPs. The camouflaged gates can perform different logic functions while maintaining an identical look to RE attackers, thus preventing them from obtaining the layout information of the IP directly from RE tools. Since it was first proposed in 2012, circuit camouflaging has become one of the hottest research topics in hardware security focusing on two fundamental problems. How to choose the types of camouflaged gates and decide where to insert them in order to simultaneously minimize the performance overhead and optimize the RE complexity？ How can an attacker de-camouflage a camouflaged circuit and complete the RE attack？ In this article, we review the evolution of circuit camouflaging through this spear and shield race. First, we introduce the design methods of four different kinds of camouflaged ceils based on true/dummy contacts, static random access memory （SRAM）, doping, and emerging devices, respectively. Then we elaborate four representative de-camouflaging attacks： brute force attack, IC testing based attack, satisfiability-based （SAT-based） attack, and the circuit partition based attack, and the corresponding countermeasures： clique-based camouflaging, CamoPerturb, AND-tree camouflaging, and equivalent class based camouflaging, respectively. We argue that the current research efforts should be on reducing overhead introduced by circuit camouflaging and defeating decamouflaging attacks. We point out that exploring features of emerging devices could be a promising direction. Finally, as a complement to circuit camouflaging, we conclude with a brief review of other state-of-the-art IP protection techniques.

Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks

Electromigration(EM)is a severe reliability issue in power grid networks.The via array possesses special EM characteristics and suffers from Joule heating and current crowding,closely related to EM violations.In this study,a power grid EM analysis method was developed to solve temperature variation effects for the via array EM.The new method is based on the temperature-aware EM model,which considers the effects of self-heating and thermal coupling of interconnected lines in a power grid.According to the model,the proposed methodology introduces a locality-driven strategy and current tracking to perform full-chip EM assessment for multilayered power grids.The results show that temperature due to Joule heating indeed has significant impacts on the via EM failure.The results further demonstrate that the proposed method might reasonably improve efficiency while ensuring the accuracy of the analysis.