The growing complexity of integrated circuits (ICs) is driving the trend of IC testing towards testing based on behavioral descriptions of register-transfer level (RTL). A behavioral description contains an algorithmi...The growing complexity of integrated circuits (ICs) is driving the trend of IC testing towards testing based on behavioral descriptions of register-transfer level (RTL). A behavioral description contains an algorithmic specification of functionality of design. It may contain little or even no information about the design’s cycle-by-cycle behavior or structural implementation. However, it usually has an interior variable to lead the process of its functional phases. This interior variable is named phase variable. The functional behavior of a digital circuit changes according to different values of a phase variable. By analyzing some ITC99 benchmark circuits, this paper presents a way to generate tests for a circuit by tracing the value change of a phase variable in the circuit.展开更多
The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms...The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.展开更多
文摘The growing complexity of integrated circuits (ICs) is driving the trend of IC testing towards testing based on behavioral descriptions of register-transfer level (RTL). A behavioral description contains an algorithmic specification of functionality of design. It may contain little or even no information about the design’s cycle-by-cycle behavior or structural implementation. However, it usually has an interior variable to lead the process of its functional phases. This interior variable is named phase variable. The functional behavior of a digital circuit changes according to different values of a phase variable. By analyzing some ITC99 benchmark circuits, this paper presents a way to generate tests for a circuit by tracing the value change of a phase variable in the circuit.
基金supported by National Natural Science Foundation of China under grant No.69733010.
文摘The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.
