With the ever-growing number of base stations(BSs)and user equipments(UEs)in ultra-dense networks(UDN),reusing the same pilot sequences among the cells is inevitable.With pilot reuse scheme,the channel estimation obta...With the ever-growing number of base stations(BSs)and user equipments(UEs)in ultra-dense networks(UDN),reusing the same pilot sequences among the cells is inevitable.With pilot reuse scheme,the channel estimation obtained at a BS contains not only the desired channel-state information(CSI)but also interference from neighboring cells,which can severely degrade CSI estimation performance and adversely affect communication performance.In this paper we consider a pilot contamination avoidance based on pilot pattern design for UDN where the pilot reuse employed and the interfering users from neighboring cells may be not at lower power levels at the BS compared to the in-cell users.We present a novel statistical interference model of sub-carriers to describe the non-deterministic interference from neighboring cells.Then,we provide a pilot pattern design model with non-uniform pilot distribution.Based on this,a pilot contamination avoidance based on pilot pattern design is proposed where pilot reuse scheme and the non-deterministic interference from neighboring cells are taken into consideration.Unlike existing interference mitigation approaches,the proposed method eliminates interference through the method of interference avoidance and can be applied to different kinds of channel estimation algorithms.Simulation results showed that the proposed approach can effectively avoid the interference and ensure the accuracy of channel estimation.展开更多
The advent of CUDA-enabled GPU makes it possible to provide cloud applications with high-performance data security services.Unfortunately,recent studies have shown that GPU-based applications are also susceptible to s...The advent of CUDA-enabled GPU makes it possible to provide cloud applications with high-performance data security services.Unfortunately,recent studies have shown that GPU-based applications are also susceptible to side-channel attacks.These published work studied the side-channel vulnerabilities of GPU-based AES implementations by taking the advantage of the cache sharing among multiple threads or high parallelism of GPUs.Therefore,for GPU-based bitsliced cryptographic implementations,which are immune to the cache-based attacks referred to above,only a power analysis method based on the high-parallelism of GPUs may be effective.However,the leakage model used in the power analysis is not efficient at all in practice.In light of this,we investigate electro-magnetic(EM)side-channel vulnerabilities of a GPU-based bitsliced AES implementation from the perspective of bit-level parallelism and thread-level parallelism in order to make the best of the localization effect of EM leakage with parallelism.Specifically,we propose efficient multi-bit and multi-thread combinational analysis techniques based on the intrinsic properties of bitsliced ciphers and the effect of multi-thread parallelism of GPUs,respectively.The experimental result shows that the proposed combinational analysis methods perform better than non-combinational and intuitive ones.Our research suggests that multi-thread leakages can be used to improve attacks if the multi-thread leakages are not synchronous in the time domain.展开更多
The advent of CUDA-enabled GPU makes it possible to provide cloud applications with high-performance data security services.Unfortunately,recent studies have shown that GPU-based applications are also susceptible to s...The advent of CUDA-enabled GPU makes it possible to provide cloud applications with high-performance data security services.Unfortunately,recent studies have shown that GPU-based applications are also susceptible to side-channel attacks.These published work studied the side-channel vulnerabilities of GPU-based AES implementations by taking the advantage of the cache sharing among multiple threads or high parallelism of GPUs.Therefore,for GPU-based bitsliced cryptographic implementations,which are immune to the cache-based attacks referred to above,only a power analysis method based on the high-parallelism of GPUs may be effective.However,the leakage model used in the power analysis is not efficient at all in practice.In light of this,we investigate electro-magnetic(EM)side-channel vulnerabilities of a GPU-based bitsliced AES implementation from the perspective of bit-level parallelism and thread-level parallelism in order to make the best of the localization effect of EM leakage with parallelism.Specifically,we propose efficient multi-bit and multi-thread combinational analysis techniques based on the intrinsic properties of bitsliced ciphers and the effect of multi-thread parallelism of GPUs,respectively.The experimental result shows that the proposed combinational analysis methods perform better than non-combinational and intuitive ones.Our research suggests that multi-thread leakages can be used to improve attacks if the multi-thread leakages are not synchronous in the time domain.展开更多
基金This work was supported in part by the Chongqing Research Program of Basic Research and Frontier Technology under Grant cstc2019jcyj-msxmX0233in part by Science and Technology Research Program of Chongqing Education Commission of China under Grant KJQN201901125,Grant KJQN201901103in part by the Scientific Research Foundation of Chongqing University of Technology under Grant 2019ZD42,Grant 2019ZD63.
文摘With the ever-growing number of base stations(BSs)and user equipments(UEs)in ultra-dense networks(UDN),reusing the same pilot sequences among the cells is inevitable.With pilot reuse scheme,the channel estimation obtained at a BS contains not only the desired channel-state information(CSI)but also interference from neighboring cells,which can severely degrade CSI estimation performance and adversely affect communication performance.In this paper we consider a pilot contamination avoidance based on pilot pattern design for UDN where the pilot reuse employed and the interfering users from neighboring cells may be not at lower power levels at the BS compared to the in-cell users.We present a novel statistical interference model of sub-carriers to describe the non-deterministic interference from neighboring cells.Then,we provide a pilot pattern design model with non-uniform pilot distribution.Based on this,a pilot contamination avoidance based on pilot pattern design is proposed where pilot reuse scheme and the non-deterministic interference from neighboring cells are taken into consideration.Unlike existing interference mitigation approaches,the proposed method eliminates interference through the method of interference avoidance and can be applied to different kinds of channel estimation algorithms.Simulation results showed that the proposed approach can effectively avoid the interference and ensure the accuracy of channel estimation.
基金This work was supported in part by National Natural Science Foundation of China(No.61632020,UI936209)Beijing National Science Foundation(No.4192067).
文摘The advent of CUDA-enabled GPU makes it possible to provide cloud applications with high-performance data security services.Unfortunately,recent studies have shown that GPU-based applications are also susceptible to side-channel attacks.These published work studied the side-channel vulnerabilities of GPU-based AES implementations by taking the advantage of the cache sharing among multiple threads or high parallelism of GPUs.Therefore,for GPU-based bitsliced cryptographic implementations,which are immune to the cache-based attacks referred to above,only a power analysis method based on the high-parallelism of GPUs may be effective.However,the leakage model used in the power analysis is not efficient at all in practice.In light of this,we investigate electro-magnetic(EM)side-channel vulnerabilities of a GPU-based bitsliced AES implementation from the perspective of bit-level parallelism and thread-level parallelism in order to make the best of the localization effect of EM leakage with parallelism.Specifically,we propose efficient multi-bit and multi-thread combinational analysis techniques based on the intrinsic properties of bitsliced ciphers and the effect of multi-thread parallelism of GPUs,respectively.The experimental result shows that the proposed combinational analysis methods perform better than non-combinational and intuitive ones.Our research suggests that multi-thread leakages can be used to improve attacks if the multi-thread leakages are not synchronous in the time domain.
基金supported in part by National Natural Science Foundation of China(No.61632020,UI936209)Beijing National Science Foundation(No.4192067).
文摘The advent of CUDA-enabled GPU makes it possible to provide cloud applications with high-performance data security services.Unfortunately,recent studies have shown that GPU-based applications are also susceptible to side-channel attacks.These published work studied the side-channel vulnerabilities of GPU-based AES implementations by taking the advantage of the cache sharing among multiple threads or high parallelism of GPUs.Therefore,for GPU-based bitsliced cryptographic implementations,which are immune to the cache-based attacks referred to above,only a power analysis method based on the high-parallelism of GPUs may be effective.However,the leakage model used in the power analysis is not efficient at all in practice.In light of this,we investigate electro-magnetic(EM)side-channel vulnerabilities of a GPU-based bitsliced AES implementation from the perspective of bit-level parallelism and thread-level parallelism in order to make the best of the localization effect of EM leakage with parallelism.Specifically,we propose efficient multi-bit and multi-thread combinational analysis techniques based on the intrinsic properties of bitsliced ciphers and the effect of multi-thread parallelism of GPUs,respectively.The experimental result shows that the proposed combinational analysis methods perform better than non-combinational and intuitive ones.Our research suggests that multi-thread leakages can be used to improve attacks if the multi-thread leakages are not synchronous in the time domain.
