Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient(SET)pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor(Fin FET)inverter chains with different driven strengths are measured at different temperatures.Three-dimensional(3D)technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature.Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk Fin FET technology,resulting in the increase of SET pulse width.On the other hand,the increase of inverter driven strength will change the layout topology,which has a complex influence on the SET temperature effects of Fin FET inverter chains.The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.